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LTC2970CUFD Datasheet(PDF) 29 Page - Linear Technology |
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LTC2970CUFD Datasheet(HTML) 29 Page - Linear Technology |
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29 / 36 page  LTC2970/LTC2970-1 29 29701fc APPLICATIO S I FOR ATIO the LTC2970 will automatically find the IDAC code that most closely approximates the TRIM pin's open-circuit voltage before enabling VOUT0. Note: The relationship between VTRIM and the converter's output is typically non-invert- ing, so be sure to set the LTC2970's CH0_a_idac_pol bit to 1 in order to allow the voltage servo feature to function properly. DC/DC converters with a TRIM pin are usually margined high or low by connecting an external resistor between the TRIM pin and either the VSENSE+ or VSENSE– pin. The relationships between these resistors and the Δ% change in the output voltage of the DC/DC converter are typically expressed as: R R R TRIM DOWN TRIM DOWN TRIM _ • % = Δ − 50 (8) R RV V R TRIM UP TRIM DC UP REF UP T _ •• % •• % = +Δ () Δ − 100 2 R RIM UP TRIM R • % 50 Δ − ⎡ ⎣ ⎢ ⎤ ⎦ ⎥ (9) where RTRIM is the resistance looking into the TRIM pin, VREF is the TRIM pin's opern-circuit output voltage and VDC is the DC/DC converter's nominal output voltage. ΔUP% and ΔDOWN% denote the percentage change in the converter's output voltage when margining up or down respectively. 2-Step Resistor Selection Procedure for DC/DC Converters with a TRIM Pin The following two-step procedure should be used to calculate values for resistors R30 and R40 shown in Figure 2. 1. Solve for R30: RRTRIM DOWN DOWN 30 50 ≤ −Δ Δ ⎛ ⎝⎜ ⎞ ⎠⎟ • % % (10) 2. Solve for R40: R V A UP DOWN REF 40 1 236 ≥+ Δ Δ ⎛ ⎝⎜ ⎞ ⎠⎟ % % • μ (11) Tracking with the LTC2970-1 A typical LTC2970-1 tracking application circuit is shown in Figure 3 (the sequence of events for tracking are described in sections 9 and 10 of the Operation section). The GPIO_0 and GPIO_1 pins are tied directly to their respective DC/DC converter RUN/SS pins. Since GPIO_CFG is pulled-up to VDD, the LTC2970-1 will automatically hold off the DC/DC converters after power-up by asserting open drain outputs GPIO_0 and GPIO_1 low. N-channel FETs Q10/11 and diodes D10/11 form unidirectional range switches around resistors R30A/31A while GPIO_CFG is high. These range switches allow the LTC2970-1’s VOUT0 and VOUT1 pins to drive the converter outputs all the way to/from ground through resistors R30B/31B. When GPIO_CFG pulls low, N-channel FETs Q10 and Q11 will turn off. R30A/31A and R30B/31B then combine in series for normal margin operation. The 100k/0.1μF low-pass filter in series with the gates of Q10/11 minimizes charge injection into the feedback nodes of the DC/DC converters when GPIO_CFG pulls low. Figure 3. LTC2970-1 Tracking Application Circuit 0.1 μF 0.1 μF LTC2970-1 I2C BUS GPIO_1 IOUT1 VOUT1 12VIN GND VDD GPIO_CFG 10k 100k 29701 F03 ALERT SCL SDA IN OUT DC/DC CONVERTER FB RUN/SS VIN VDC1 R11 Q10, Q11: 2N7002 D10, D11: MMBD4448V *SOME DETAILS OMITTED FOR CLARITY R41 R21 R31A Q11 D11 R31B GPIO_0 IOUT0 VOUT0 IN OUT DC/DC CONVERTER FB RUN/SS VIN VDC0 R10 R40 R20 R30A Q10 D10 R30B 8V TO 15V 0.1 μF |
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