MPC8306S datasheet(5/70 Pages) FREESCALE

5 / 70 page

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

Overview

— Six groups of interrupts with programmable priority

— External and internal interrupts directed to host processor

— Unique vector number for each interrupt source

•

Universal serial bus (USB) dual-role controller

— Designed to comply with Universal Serial Bus Revision 2.0 Specification

— Supports operation as a stand-alone USB host controller

— Supports operation as a stand-alone USB device

— Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations.

Low speed is only supported in host mode.

•

Dual I2C interfaces

— Two-wire interface

— Multiple-master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

—I2C1 can be used as the boot sequencer

•

DMA Engine

— Support for the DMA engine with the following features:

– Sixteen DMA channels

– All data movement via dual-address transfers: read from source, write to destination

– Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations

– Channel activation via one of two methods (for both the methods, one activation per

execution of the minor loop is required):

– Explicit software initiation

– Initiation via a channel-to-channel linking mechanism for continuous transfers

(independent channel linking at end of minor loop and/or major loop)

– Support for fixed-priority and round-robin channel arbitration

– Channel completion reported via optional interrupt requests

— Support for scatter/gather DMA processing

•

DUART

— Two 2-wire interfaces (RxD, TxD)

– The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

•

Serial peripheral interface (SPI)

— Master or slave support

•

Power managemnt controller (PMC)

— Supports core doze/nap/sleep/ power management

— Exits low power state and returns to full-on mode when

– The core internal time base unit invokes a request to exit low power state

MPC8306S Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc

MPC8306S Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL