MPC8306S datasheet(58/70 Pages) FREESCALE

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MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

Clocking

NOTE

Core VCO frequency = core frequency

 VCO divider. The VCO divider

(RCWL[COREPLL[0:1]]), must be set properly so that the core VCO

frequency is in the range of 400–800 MHz.

20.4

QUICC Engine PLL Configuration

The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. The

following table shows the multiplication factor encodings for the QUICC Engine PLL.

0001

1.5:1

 2

0001

1.5:1

 4

0001

1.5:1

 8

0001

1.5:1

 8

0010

2:1

 2

0010

2:1

 4

0010

2:1

 8

0010

2:1

 8

0010

2.5:1

 2

0010

2.5:1

 4

0010

2.5:1

 8

0010

2.5:1

 8

0011

3:1

 2

0011

3:1

 4

0011

3:1

 8

0011

3:1

 8

Table 52. QUICC Engine PLL Multiplication Factors

RCWL[CEPMF]

RCWL[CEPDF]

QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/

(1 + RCWL[CEPDF)

00000–00001

Reserved

00010

 2

00011

 3

00100

 4

00101

 5

00110

 6

Table 51. e300 Core PLL Configuration (continued)

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO Divider

0-1

2-5

MPC8306S Datasheet(PDF) 58 Page - Freescale Semiconductor, Inc

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