ADAS1000BSTZ datasheet(43/80 Pages) AD

43 / 80 page

Data Sheet

ADAS1000/ADAS1000-1/ADAS1000-2

Rev. A | Page 43 of 80

While these experiments validate the pace algorithm over a

confined set of circumstances and conditions, they do not

replace end system verification of the pacer algorithm. This

can be performed in only the end system, using the system

manufacturer’s specified cables and validation data set.

EVALUATING PACE DETECTION PERFORMANCE

ECG simulators offer a convenient means of studying the

performance and ability of the ADAS1000 to capture pace

signals over the range of widths and heights defined by the

various regulatory standards. While the pace detection algorithm

of the ADAS1000 is designed to conform to medical instrument

standards, some simulators put out signals wider (or narrower)

than called for in the standards, and these will be rejected as

invalid by the algorithm of the ADAS1000.

The pace width acceptance window of the ADAS1000 is the

tightest at the 2 ms limit. If this proves problematic, margin can

be obtained by reducing the master clock frequency. As an

example, using an 8.000 MHz crystal in place of the

recommended 8.192 MHz crystal increases the high limit of the

pace acceptance window from 2.000 ms to 2.048 ms. The low

limit also increases; however, this does not impair the ability of

the algorithm to detect 100 µs pace pulses.

Changing the clock frequency affects all of the other ADAS1000

frequency-related functions. Continuing with the 8.000 MHz

example, the −3 dB frequencies for ECG scales by a factor of

8000/8192, with 40 Hz becoming 39.06 Hz and 150 Hz becoming

146.5 Hz, which are both still well within regulatory requirements.

The respiration and ac leads-off frequencies, as well as the

output data rates, also scale by the same 8000/8192 fraction.

PACE LATENCY

The pace algorithm always examines 128 kHz, 16-bit ECG data,

regardless of the selected frame rate and ECG filter setting. A

pace pulse is qualified when a valid trailing edge is detected and

is flagged in the next available frame header. Pace and ECG data

is always correctly time-aligned at the 128 kHz frame rate, but

the additional filtering inherent in the slower frame rates delays

the frame's ECG data relative to the pace pulse flag. These

delays are summarized in Table 14 and must be taken into

account to enable correct positioning of the pace event relative

to the ECG data.

There is an inherent one-frame-period uncertainty in the exact

location of the pace trailing edge.

PACE DETECTION VIA SECONDARY SERIAL

INTERFACE (ADAS1000 AND ADAS1000-1 ONLY)

The ADAS1000/ADAS1000-1 provide a second serial interface

for users who wish to implement their own pace detection

schemes. This interface is configured as a master interface. It

provides ECG data at the 128 kHz data rate only. The purpose

of this interface is to allow the user to access the ECG data at a

rate sufficient to allow them to run their own pace algorithm,

while maintaining all the filtering and decimation of the ECG

data that the ADAS1000/ADAS1000-1 offer on the standard

serial interface (2 kHz and 16 kHz data rates). This dedicated

pace interface uses three of the four GPIO pins, leaving one

GPIO pin available even when the secondary serial interface is

enabled. Note that the on-chip digital calibration to ensure

channel gain matching does not apply to data that is available

on this interface. This interface is discussed in more detail in

the Secondary Serial Interface section.

FILTERING

Figure 72 shows the ECG digital signal processing. The ADC

sample rate is programmable. In high performance mode, it

is 2.048 MHz; in low power mode, the sampling rate is reduced

to 1.024 MHz. The user can tap off framing data at one of three

data rates, 128 kHz, 16 kHz, or 2 kHz. Note that although the

data-word width is 24 bits for the 2 kHz and 16 kHz data rate,

the usable bits are 19 and 18, respectively.

The amount of decimation depends on the selected data rate,

with more decimation for the lower data rates.

Four selectable low-pass filter corners are available at the 2 kHz

data rate.

Filters are cleared by a reset. Table 14 shows the filter latencies

at the different data rates.

Figure 72. ECG Channel Filter Signal Flow

2.048MHz

ADC DATA

14-BITS

2.048MHz

128kHz

–3dB AT 13kHz

ACLO

CARRIER

NOTCH

2kHz

AC LEAD-OFF

DETECTION

PACE

DETECTION

128kHz DATA RATE

16-BITS WIDE

AVAILABLE DATA RATE

CHOICE OF 1:

40Hz

150Hz

250Hz

(PROGRAMMABLE BESSEL )

~7Hz

16kHz DATA RATE

24-BITS WIDE

18 USABLE BITS

2kHz DATA RATE

24-BITS WIDE

19 USABLE BITS

128kHz

16kHz

–3dB AT 3.5kHz

2kHz

–3dB AT 450Hz

16kHz

CALIBRATION

31.25Hz DATA RATE

24-BITS WIDE

~22 USABLE BITS

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