PIC16F1503 datasheet(71/340 Pages) MICROCHIP

71 / 340 page

 2011 Microchip Technology Inc.

Preliminary

DS41607A-page 71

PIC16(L)F1503

7.6.6

PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 7-6.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE, of the INTCON

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

U-0

R/W-0/0

U-0

R/W-0/0

U-0

—

C2IF

C1IF

—

BCL1IF

NCO1IF

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6

C2IF: Numerically Controlled Oscillator Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 5

C1IF: Numerically Controlled Oscillator Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 4

Unimplemented: Read as ‘0’

bit 3

BCL1IF: MSSP Bus Collision Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 2

NCO1IF: Numerically Controlled Oscillator Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 1-0

Unimplemented: Read as ‘0’

PIC16F1503 Datasheet(PDF) 71 Page - Microchip Technology

PIC16F1503 Datasheet(HTML) 71 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL