EM3027

Copyright

 2013, EM Microelectronic-Marin SA

3027-DS.doc, Version 8.0, 25-Jan-13

18

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8.7.2

Clock Output

Output clock frequency is selected by FD1, FD0 bits in EEctrl register.

FD1

FD0

Select Clock Output

Description

0

0

32.768 kHz

From crystal oscillator, without

frequency compensation

0

1

1024 Hz

With frequency compensation

1

0

32 Hz

1

1

1 Hz

Table 12: Output Clock frequency selection

8.7.3

Configuration Registers

All the configuration data from EEPROM (i.e. EEctrl, XTalOffset, Qcoef, TurnOver, EEData) is hold in configuration

registers.

Data from EEPROM is loaded to these registers during power-up sequence and is refr

eshed each hour, if ‘Configuration

Registers refresh’ feature is enabled (EERefOn = ‘1’).

Regular refresh of Configuration Registers prevents their content to be corrupted by strongly polluted electrical environment

(EMC problems, disturbed power supply, etc.).

It is recommended to enable ‘Configuration Registers refresh’ feature.

8.7.4

EEPROM User Memory

Two bytes of the memory are dedicated for the application (addresses 0x28 and 0x29).

8.8

RAM User Memory

RAM user memory size is 8 bytes (addresses 0x38 to 0x3F). The state of the RAM data after power-up is undefined.

8.9

Status Register

The purpose of EEBusy bit is to inform the user about current status of the EEPROM operations.

EEBusy

– status of EEPROM controller (if EEBusy = ‘1’, then Configuration Registers refresh or EEPROM write is in

progress)

The purpose of the following status bits is to record status of power supply voltage and Self-Recovery system/System reset

behaviour.

PON

– status of Power-ON

VLOW1

– status of Vlow1 voltage detection

VLOW2

– status of Vlow2 voltage detection

SR

– status of the Self-Recovery system/System reset

If one of these status bits is set, it can be cleared only by writing

‘0’, there is no automatic reset if the set condition

disappears.

8.10

Interrupts

There are five interrupt sources which can output an interrupt on (INT and/or IRQ/CLKOUT) pins. The request

is generated when at least one of IRQflags goes to ‘1’ (OR function).

AF

– interrupt is provided when Watch time reaches Alarm time settings and comparison is enabled

TF

– interrupt is provided when Timer reaches ZERO

V1F

– interrupt is provided when supply voltage is below Vlow1 (when VLOW1 status bit is set)

V2F

– interrupt is provided when supply voltage is below Vlow2 (when VLOW2 status bit is set)

SRF

– interrupt is provided when Self-Recovery system invoked internal reset (when SR status bit is set)

Each interrupt source has its own interrupt enable (AIntE, TIntE, V1IntE, V2IntE, SRIntE). When the interrupt

enable is ‘1’

then the appropriate interrupt source is enabled.