DAC5675

SLAS352C − DECEMBER 2001 − REVISED AUGUST 2004

6

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detailed description (continued)

digital inputs

The DAC5675 comprises a low voltage differential signaling (LVDS) bus input interface. The LVDS features a

low differential voltage swing with low constant power consumption (~4 mA per complementary data input)

across frequency. The differential characteristic of LVDS allows for high-speed data transmission with low

electromagnetic interference (EMI) levels. The LVDS input minimum and maximum input threshold table lists

the LVDS input levels. Figure 2 shows the equivalent complementary digital input interface for the DAC5675,

valid for pins D[13..0]A and D[13..0]B. Note that the LVDS interface features internal 110-

Ω resistors for proper

termination. Figure 3 shows the LVDS input timing measurement circuit and waveforms. A common mode level

of 1.2 V and a differential input swing of 0.8 V is applied to the inputs.

Internal

Digital In

D[13:0]A

D[13:0]B

AGND

AVDD

Internal

Digital In

D[13:0]A

D[13:0]B

DAC5675

DAC5675

100-

Ω

Termination

Resistor

Figure 2. LVDS Digital Equivalent Input

VB

VA

VA,B

1.4 V

1 V

0.4 V

−0.4 V

0 V

Logical Bit

Equivalent

0

1

AGND

AVDD

DAC5675

V

V

2

VB

VA

VA,B

Figure 3. LVDS Timing Test Circuit and Input Test Levels