AD9549APCBZ datasheet(4/76 Pages) AD

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AD9549

Rev. D | Page 4 of 76

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%. AVSS = 0 V, DVSS = 0 V, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY VOLTAGE

DVDD_I/O (Pin 1)

3.135

3.30

3.465

DVDD (Pin 3, Pin 5, Pin 7)

1.71

1.80

1.89

AVDD3 (Pin 14, Pin 46, Pin 47, Pin 49)

3.135

3.30

3.465

AVDD3 (Pin 37)

1.71

3.30

3.465

Pin 37 is typically 3.3 V, but can be set to 1.8 V

AVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29,

Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53)

1.71

1.80

1.89

SUPPLY CURRENT

IAVDD3 (Pin 14)

4.7

5.6

REFA, REFB buffers

IAVDD3 (Pin 37)

3.8

4.5

CMOS output clock driver at 3.3 V

IAVDD3 (Pin 46, Pin 47, Pin 49)

DAC output current source, fS = 1 GSPS

IAVDD (Pin 36, Pin 42)

FDBK_IN input, HSTL output clock driver

(output doubler turned on)

IAVDD (Pin 11)

REFA and REFB input buffer 1.8 V supply

IAVDD (Pin 19, Pin 23 to Pin 26, Pin 29,

Pin 30, Pin 44, Pin 45)

215

281

Aggregate analog supply, including system

clock PLL

IAVDD (Pin 53)

DAC power supply

IDVDD (Pin 3, Pin 5, Pin 7)

254

265

Digital core

IDVDD_I/O (Pin 1)

Digital I/O (varies dynamically)

LOGIC INPUTS (Except Pin 32)

Pin 9, Pin 10, Pin 54 to Pin 61, Pin 63, Pin 64

Input High Voltage (VIH)

2.0

DVDD_I/O

Input Low Voltage (VIL)

DVSS

0.8

Input Current (IINH, IINL)

±60

±200

µA

At VIN = 0 V and VIN = DVDD_I/O

Maximum Input Capacitance (CIN)

CLKMODESEL (Pin 32) LOGIC INPUT

Pin 32 only

Input High Voltage (VIH)

1.4

AVDD

Input Low Voltage (VIL)

AVSS

0.4

Input Current (IINH, IINL)

−18

−50

µA

At VIN = 0 V and VIN = AVDD

Maximum Input Capacitance (CIN)

LOGIC OUTPUTS

Pin 62 and the following bidirectional pins:

Pin 9, Pin 10, Pin 54, Pin 55, Pin 63

Output High Voltage (VOH)

2.7

DVDD_I/O

IOH = 1 mA

Output Low Voltage (VOL)

DVSS

0.4

IOL = 1 mA

REFERENCE INPUTS

Pin 12, Pin 13, Pin 15, Pin 16

Input Capacitance

Input Resistance

8.5

11.5

14.5

kΩ

Differential at Register 0x040F[1:0] = 00

Differential Operation

Common Mode Input Voltage1

1.5

(Applicable When DC-Coupled)

AVDD3 −

0.2

Differential operation; note that LVDS signals

must be ac-coupled

Differential Input Voltage Swing1

500

mV p-p

Differential operation

Single-Ended Operation

Input Voltage High (VIH)

2.0

AVDD3

Input Voltage Low (VIL)

AVSS

0.8

Threshold Voltage

AVDD3 −

0.66

AVDD3 −

0.82

AVDD3 −

0.98

possible)

Input Current

Single-ended operation

FDBK_IN INPUT

Pin 40, Pin 41

Input Capacitance

Input Resistance

kΩ

Differential

Differential Input Voltage Swing2

225

mV p-p

−12 dBm into 50 Ω; must be ac-coupled

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