AD9549APCBZ datasheet(71/76 Pages) AD

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AD9549

Rev. D | Page 71 of 76

Table 127.

Bits

Bit Name

Description

[7:6]

Part version

01b = AD9549, Revision A

00b = AD9549, Revision 0

[5:0]

Reserved

N/A

Table 128.

Bits

Bit Name

Description

[7:0]

DPLL phase offset

This register controls the static time offset of the PFD (phase frequency detector) in closed-loop mode.

It has no effect when the DPLL is open.

Table 129.

Bits

Bit Name

Description

[13:8]

DPLL phase offset

This register controls the static time offset of the PFD (phase frequency detector) in closed-loop mode.

It has no effect when the DPLL is open.

Table 130.

Bits

Bit Name

Description

[7:0]

DAC full-scale current

DAC full-scale current, Bits[7:0]. See the DAC Output section.

Table 131.

Bits

Bit Name

Description

[9:8]

DAC full-scale current

DAC full-scale current, Bits[9:8]. See Register 0x040B.

Table 132.

Bits

Bit Name

Description

[7:2]

Reserved

Reserved.

[1:0]

DC input level

This register sets the dc bias level for the reference inputs. The value should be chosen such that V

IH is

as close as possible to, but does not exceed, 3.3 V.

00 = VDD3 − 800 mV.

01 = VDD3 − 400 mV.

10 = VDD3 − 1.6 V.

11 = VDD3 − 1.2 V.

HARMONIC SPUR REDUCTION (REGISTER 0x0500 TO REGISTER 0x0509)

See the Harmonic Spur Reduction section.

AD9549APCBZ Datasheet(PDF) 71 Page - Analog Devices

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