AD7631BSTZ datasheet(25/32 Pages) AD

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AD7631

Rev. A | Page 25 of 32

18-Bit Interface (Master or Slave)

The 18-bit interface is selected by setting MODE[1:0] = 0.

In this mode, the data output is straight binary.

16-Bit and 8-Bit Interface (Master or Slave)

In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2)

interfaces, Pin A0 and Pin A1 allow a glueless interface to a

16- or 8-bit bus, as shown in Figure 40 (refer to Table 7 for more

details). By connecting Pin A0 and Pin A1 to an address line(s),

the data can be read in two words for a 16-bit interface or three

bytes for an 8-bit interface. This interface can be used in both

master and slave parallel reading modes.

CS, RD

D[17:2]

HI-Z

HIGH

WORD

LOW

WORD

HI-Z

t12

t13

HIGH

BYTE

MID

BYTE

LOW

BYTE

D[17:10]

t12

HI-Z

t12

Figure 40. 8-Bit and16-Bit Parallel Interface

SERIAL INTERFACE

The AD7631 is configured to use the serial interface

when MODE[1:0]= 3. The AD7631 has a serial interface

(SPI-compatible) multiplexed on the data pins D[17:4].

Data Interface

The AD7631 outputs 18 bits of data, MSB first, on the SDOUT pin.

This data is synchronized with the 18 clock pulses provided on

the SDCLK pin. The output data is valid on both the rising and

falling edge of the data clock.

Serial Configuration Interface

The AD7631 can only be configured through the serial

configuration register in serial mode as the serial configuration

pins are also multiplexed on the data pins D[17:14]. See the

Hardware Configuration section and the Software Configuration

section for more information.

MASTER SERIAL INTERFACE

The pins multiplexed on D[12:4] and used for master serial

interface are: DIVSCLK[1:0], EXT/INT, INVSYNC, INVSCLK,

RDC, SDOUT, SDCLK, and SYNC.

Internal Clock (MODE[1:0] = 3, EXT/INT = Low)

The AD7631 is configured to generate and provide the serial

data clock, SDCLK, when the EXT/INT pin is held low. The

AD7631 also generates a SYNC signal to indicate to the host

when the serial data is valid. The SDCLK and the SYNC signals

can be inverted, if desired, using the INVSCLK and INVSYNC

inputs, respectively. Depending on the input, RDC, the data

can be read during the following conversion or after each

conversion.

and

show detailed timing

diagrams of these two modes.

Figure 41

Figure 42

Read During Convert (RDC = High)

Setting RDC = high allows the master read (previous

conversion result) during conversion mode. Usually, because

the AD7631 is used with a fast throughput, this mode is the

most recommended serial mode. In this mode, the serial clock

and data switch on and off at appropriate instances, minimizing

potential feedthrough between digital activity and critical

conversion decisions. In this mode, the SDCLK period changes

because the LSBs require more time to settle, and the SDCLK is

derived from the SAR conversion cycle. In this mode, the

AD7631 generates a discontinuous SDCLK of two different

periods, and the host should use an SPI interface.

Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3])

Setting RDC = low allows the read after conversion mode.

Unlike the other serial modes, the BUSY signal returns low after

the 18 data bits are pulsed out and not at the end of the conversion

phase, resulting in a longer BUSY width (see Table 4 for BUSY

timing specifications). The DIVSCLK[1:0] inputs control the

SDCLK period and SDOUT data rate. As a result, the maximum

throughput cannot be achieved in this mode. In this mode, the

AD7631 also generates a discontinuous SDCLK; however, a

fixed period and hosts supporting both SPI and serial ports can

also be used.

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