AD7631BSTZ datasheet(26/32 Pages) AD

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AD7631

Rev. A | Page 26 of 32

EXT/INT = 0

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

D17

D16

BUSY

SYNC

SDCLK

SDOUT

CNVST

CS, RD

t23

t18

t15

t14

t17

t22

t16

t25

t26

t24

t27

t19

t20 t21

MODE[1:0] = 3

Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)

BUSY

SYNC

SDCLK

SDOUT

D17

D16

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

CNVST

CS, RD

EXT/INT = 0

t23

t22

t16

t15

t14

t29

t19

t21

t20

t18

t28

t30

t24

t25

t26

t27

MODE[1:0] = 3

Figure 42. Master Serial Data Timing for Reading (Read After Convert)

SLAVE SERIAL INTERFACE

The pins multiplexed on D[13:6] used for slave serial

interface are: EXT/INT, INVSCLK, SDIN, SDOUT, SDCLK,

and RDERROR.

External Clock (MODE[1:0] = 3, EXT/INT = High)

Setting the EXT/INT = high allows the AD7631 to accept an

externally supplied serial data clock on the SDCLK pin. In this

mode, several methods can be used to read the data. The external

serial clock is gated by CS. When CS and RD are both low, the

data can be read after each conversion or during the following

conversion. A clock can be either normally high or normally

low when inactive. For detailed timing diagrams, see

and

Figure 44

Figure 45

While the AD7631 is performing a bit decision, it is important

that voltage transients be avoided on digital input/output pins,

or degradation of the conversion result may occur. This is

particularly important during the last 550 ns of the conversion

phase because the AD7631 provides error correction circuitry

that can correct for an improper bit decision made during

the first part of the conversion phase. For this reason, it is

recommended that any external clock provided is a

discontinuous clock that transitions only when BUSY is low,

or, more importantly, that it does not transition during the

last 450 ns of BUSY high.

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