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Single-Chip Voice Recording & Playback Device for Multiple 40- to 60-Second Messages

Functional Description

The APR9600 block diagram is included in order to give

understanding of the APR9600 i

i nternal architecture. At the

left hand side of the diagram are the analog inputs. A differ-

ential microphone amplifier, including integrated AGC, is

included on-chip for applications requiring its use. The ampli-

fied microphone signal is fed into the device by connecting

the Ana_Out pin to the Ana_In pin through an external DC

blocking capacitor. Recording can be fed directly into the

Ana_In pin through a DC blocking capacitor, however, the

connection between Ana_In and Ana_Out is still required for

playback. The next block encountered by the input signal is

the internal anti-aliasing filter. The filter automatically adjusts

its response according to the sampling frequency selected so

Shannon’s Sampling Theorem is satisfied. After anti-aliasing

filtering is accomplished the signal is ready to be clocked into

the memory array. This storage is accomplished through a

combination of the Sample and Hold circuit and the Analog

Write/Read circuit. These circuits are clocked by either the

Internal Oscillator or an external clock source. When play-

back is desired the previously stored recording is retrieved

from memory, low pass filtered, and amplified as shown on

the right hand side of the diagram. The signal can be heard

by connecting a speaker to the SP+ and SP- pins. Chip-wide

management is accomplished through the device control

block shown in the upper right hand corner. Message man-

agement is controlled through the message control block rep-

resented in the lower center of the block diagram. More detail

on actual device application can be found in the Sample

Applications section. More detail on sampling control can be

found in the Sample Rate and Voice Quality section. More

detail on message management and device control can be

found in the Message Management section.

Figure 2 APR9600 Block Diagram

Internal

Oscillator

Anti-Aliasing

Filter

Sample & Hold

Circuit

Low Pass

Filter

Analog Write &

Read Circuits

256k Cell

Flash EPROM

Analog Storage

Array

Message Decoders

Message Control

Power Supplies

Automatic Gain

Control (AGC)

Pre-

Amp

Amp

Mux

OscR

ExtClk

Ana_In

Ana_Out

MicIn

MicRef

AGC

VCC VCCA VSSD VSSA

/M1_Message /M2_Next /M3 /M4 /M5 /M6

/M7_END

/M8_Option

MSEL2

MSEL1

SP+

SP-

BE

/Busy

/Strobe

/CE

/RE

Device Control

APR9600

APLUS