PIC18F242 datasheet(78/332 Pages) MICROCHIP

78 / 332 page

PIC18FXX2

DS39564C-page 76

INTCON2 REGISTER

R/W-1

U-0

R/W-1

U-0

R/W-1

RBPU

INTEDG0

INTEDG1

INTEDG2

—TMR0IP

—RBIP

bit 7

bit 0

bit 7

RBPU: PORTB Pull-up Enable bit

= All PORTB pull-ups are disabled

= PORTB pull-ups are enabled by individual port latch values

bit 6

INTEDG0:External Interrupt0 Edge Select bit

= Interrupt on rising edge

= Interrupt on falling edge

bit 5

INTEDG1: External Interrupt1 Edge Select bit

= Interrupt on rising edge

= Interrupt on falling edge

bit 4

INTEDG2: External Interrupt2 Edge Select bit

= Interrupt on rising edge

= Interrupt on falling edge

bit 3

Unimplemented: Read as '0'

bit 2

TMR0IP: TMR0 Overflow Interrupt Priority bit

= High priority

= Low priority

bit 1

Unimplemented: Read as '0'

bit 0

RBIP: RB Port Change Interrupt Priority bit

= High priority

= Low priority

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

PIC18F242 Datasheet(PDF) 78 Page - Microchip Technology

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