PIC18F242 datasheet(174/332 Pages) MICROCHIP

174 / 332 page

PIC18FXX2

DS39564C-page 172

16.2

USART Asynchronous Mode

In this mode, the USART uses standard non-return-to-

zero (NRZ) format (one START bit, eight or nine data

bits and one STOP bit). The most common data format

is 8-bits. An on-chip dedicated 8-bit baud rate genera-

tor can be used to derive standard baud rate frequen-

cies from the oscillator. The USART transmits and

receives the LSb first. The USART’s transmitter and

receiver are functionally independent, but use the

same data format and baud rate. The baud rate gener-

ator produces a clock, either x16 or x64 of the bit shift

rate, depending on bit BRGH (TXSTA<2>). Parity is not

supported by the hardware, but can be implemented in

software

(and

stored

the

ninth

data

bit).

Asynchronous mode is stopped during SLEEP.

Asynchronous mode is selected by clearing bit SYNC

(TXSTA<4>).

The USART Asynchronous module consists of the

following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

16.2.1

USART ASYNCHRONOUS

TRANSMITTER

The USART transmitter block diagram is shown in

Figure 16-1. The heart of the transmitter is the Transmit

(serial) Shift Register (TSR). The shift register obtains

its data from the read/write transmit buffer, TXREG. The

TXREG register is loaded with data in software. The

TSR register is not loaded until the STOP bit has been

transmitted from the previous load. As soon as the

STOP bit is transmitted, the TSR is loaded with new

data from the TXREG register (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCY), the TXREG register is empty and

flag bit TXIF (PIR1<4>) is set. This interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

( PIE1<4>). Flag bit TXIF will be set, regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicated the sta-

tus of the TXREG register, another bit, TRMT

(TXSTA<1>), shows the status of the TSR register. Sta-

tus bit TRMT is a read-only bit, which is set when the

TSR register is empty. No interrupt logic is tied to this

bit, so the user has to poll this bit in order to determine

if the TSR register is empty.

To set up an asynchronous transmission:

Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired,

set bit BRGH (Section 16.1).

Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

If interrupts are desired, set enable bit TXIE.

If 9-bit transmission is desired, set transmit bit

TX9. Can be used as address/data bit.

Enable the transmission by setting bit TXEN,

which will also set bit TXIF.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Load data to the TXREG register (starts

transmission).

FIGURE 16-1:

USART TRANSMIT BLOCK DIAGRAM

Note 1: The TSR register is not mapped in data

memory, so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

is set.

Note:

TXIF is not cleared immediately upon load-

ing data into the transmit buffer TXREG.

The flag bit becomes valid in the second

instruction

cycle

following

the

load

instruction.

TXIF

TXIE

Interrupt

TXEN

Baud Rate CLK

SPBRG

Baud Rate Generator

TX9D

MSb

LSb

Data Bus

TXREG Register

TSR Register

(8)

TX9

TRMT

SPEN

RC6/TX/CK pin

Pin Buffer

and Control

• • •

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