Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

AS5132 Datasheet(PDF) 6 Page - ams AG

Part # AS5132
Description  360 Step Programmable High Speed Magnetic Rotary Encoder
PDF  27 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS5132 Datasheet(HTML) 6 Page - ams AG

Back Button AS5132 Datasheet HTML 2Page - ams AG AS5132 Datasheet HTML 3Page - ams AG AS5132 Datasheet HTML 4Page - ams AG AS5132 Datasheet HTML 5Page - ams AG AS5132 Datasheet HTML 6Page - ams AG AS5132 Datasheet HTML 7Page - ams AG AS5132 Datasheet HTML 8Page - ams AG AS5132 Datasheet HTML 9Page - ams AG AS5132 Datasheet HTML 10Page - ams AG Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 27 page
background image
www.ams.com
Revision 1.4
6 - 27
AS5132
Datasheet - Electrical Character i s t ics
6.5 DC Characteristics of Digital Inputs
CMOS Inputs COM/INC, CSN, CLK, DIO, DIR
6.6 DC Characteristics of Digital Outputs
CMOS Outputs S, U_A, V_B, W_I, PWM, DIO
6.7 Timing Characteristics
Symbol
Parameter
Min
Typ
Max
Units
Note
VIH
High level input voltage
0.7*VDDP
VDDP
V
COM/INC refer to VDD
VIL
Low level input voltage
0
0.3*VDDP
V
ILEAK
Input leakage current
1
µA
Symbol
Parameter
Min
Typ
Max
Units
Note
VOH
High level output voltage
VDDP-0.5
VDDP
V
PWM and S have 8mA output load,
DIO has 4mA output load.
VDD-0.5
VDD
U_A, V_B, W_I have 4mA output load.
VOL
Low level output voltage
0
VSS+0.4
V
PWM and S have 8mA output load,
DIO, U_A, V_B, W_I has 4mA output load.
CL
Capacitive load
35
pF
Symbol
Parameter
Conditions
Min
Typ
Max
Units
fCLK
Clock Frequency
Normal operation
5
6
MHz
fCLKP
Clock Frequency programming
During OTP programming
200
650
kHz
t1
Chip select to positive edge of CLK
15
ns
t2
Setup time command bit,
Data valid to positive edge of CLK
30
ns
t3
Hold time command bit,
Data valid after positive edge of CLK
30
ns
t4
Float time,
Last command bit to negative edge of CLK
30
ns
t5
Transfer time,
Negative edge to valid data
30
ns
t6
Last CLK to positive edge CSN
30
ns
tCLK
Clock period
167
200
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com