13

TS68C429A

2120A–HIREL–08/02

Figure 7. Interrupt Cycle (IEIxx = 1)

Notes:

1. If UDS = 1, D15-D8 stay hi-z else D15-D8 drive the bus with a stable unknown value.

2. If IEOxx goes low, neither vector nor DTACK are generated, else IEOxx stays inactive and a vector is generated (D7-D0 and

DTACK).

Table 8. Timing Characteristic

Number

Symbol

Parameter

Min

Max

T/G

(1)

Unit

1t

AVCSL

Address valid to CS low

0

-

T

ns

R/W valid to CS low

0

-

T

ns

3t

DIVDSL

Data in valid to LDS/UDS low

0

-

T

ns

4t

SVCL

CS, LDS/UDS, IACKxx valid to CLK-SYS low

5

-

T

ns

CLK-SYS low to DTACK low

-

45

T

ns

6t

CLDOV

CLK-SYS low to data out valid

-

50

T

ns

7t

DKLDOV

DTACK low to data out valid

-

10

G

ns

CS or LDS/UDS or IACKxx high to DTACK high

-

35

G

ns

9t

SHDXZ

CS or LDS/UDS or IACKxx high to DTACK hi-z

-

50

G

ns

10

t

SHDOZ

CS or LDS/UDS or IACKxx high to data out hi-z

-

25

G

ns

11

IEIxx or IACKxx low to IEOxx low

-

35

T

ns

12

t

IKHIOH

IACKxx high to IEOxx high

-

40

T

ns

13

t

IILDKL

IEIxx low to DTACK low

-

40

T

ns

14

IEIxx low to data out valid

-

45

T

ns

15

t

SH

CS, IACKxx, LDS/UDS inactive time

15

-

T

ns

16

t

DKLSH

DTACK low to CS or LDS/UDS or IACKxx high

0

-

G

ns

17

CS or LDS/UDS high to address hold time

0

-

G

ns