TS68C429AMFBSLASHC datasheet(28/43 Pages) ATMEL

28 / 43 page

TS68C429A

2120A–HIREL–08/02

• Register Description

Any internal status change that induces a bit to be set in the status-register will generate

an interrupt if this cause is enabled by the Mask-register and if no highest priority cause

is already activated or pending.

For the receiver blocks, the priority is programmable (see interrupt vector number

description). For the transmitter block, the End-of-transmission has higher priority than

FIFO-empty and channel 1 has higher priority than channel 2 that has higher priority

than channel 3.

The RX wrong parity bit can be set only if self-test register bit 0 is set to 1.

The user has to check which receiver has it receiver control register bit 7 set to 1.

At the end of the interrupt procedure, the user must reset RX wrong parity bit to 0.

RX wrong parity is the highest interrupt priority source for the receiver part of the MRT.

• The Mask Register

The mask register is accessible for reading and writing operations. The mask register is

used to disable interrupt source. The bit order is the same as in the status register. A “0”

indicates that this source is disable, a “1” enables an interrupt for this source.

Figure 24. Mask Register

• The Base Register

The base register is only accessible for writing operations by the user. The base register

must be programmed at the initialization phase. It contains the base for the vector gen-

eration during an interrupt acknowledge. This allows the use of several peripherals. If

not programmed interrupt vector is set to $OF.

TS68C429AMFB/C Datasheet(PDF) 28 Page - ATMEL Corporation