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R5F110ME Datasheet(PDF) 67 Page - Renesas Technology Corp

Part # R5F110ME
Description  RENESAS MCU
PDF  153 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F110ME Datasheet(HTML) 67 Page - Renesas Technology Corp

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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 °C)
R01DS0192EJ0200 Rev. 2.00
Page 67 of 149
Feb 21, 2014
Note 1.
The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2.
The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Fast mode: Cb = 320 pF, Rb = 1.1 k
(2)
I2C fast mode
(TA = -40 to +85 °C, 1.8 V VDD 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
LS (low-speed main)
Mode
LV (low-voltage main)
Mode
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
SCLA0 clock
frequency
fSCL
Fast mode:
fCLK
 3.5 MHz
2.7 V
 VDD  3.6 V
0
400
0
400
0
400
kHz
1.8 V
 VDD  3.6 V
0
400
0
400
0
400
kHz
Setup time of restart
condition
tSU: STA
2.7 V
 VDD  3.6 V
0.6
0.6
0.6
s
1.8 V
 VDD  3.6 V
0.6
0.6
0.6
s
Hold time Note 1
tHD: STA
2.7 V
 VDD  3.6 V
0.6
0.6
0.6
s
1.8 V
 VDD  3.6 V
0.6
0.6
0.6
s
Hold time when
SCLA0 = “L”
tLOW
2.7 V
 VDD  3.6 V
1.3
1.3
1.3
s
1.8 V
 VDD  3.6 V
1.3
1.3
1.3
s
Hold time when
SCLA0 = “H”
tHIGH
2.7 V
 VDD  3.6 V
0.6
0.6
0.6
s
1.8 V
 VDD  3.6 V
0.6
0.6
0.6
s
Data setup time
(reception)
tSU: DAT
2.7 V
 VDD  3.6 V
100
100
100
ns
1.8 V
 VDD  3.6 V
100
100
100
ns
Data hold time
(transmission) Note 2
tHD: DAT
2.7 V
 VDD  3.6 V
0
0.9
0
0.9
0
0.9
s
1.8 V
 VDD  3.6 V
0
0.9
0
0.9
0
0.9
s
Setup time of stop
condition
tSU: STO
2.7 V
 VDD  3.6 V
0.6
0.6
0.6
s
1.8 V
 VDD  3.6 V
0.6
0.6
0.6
s
Bus-free time
tBUF
2.7 V
 VDD  3.6 V
1.3
1.3
1.3
s
1.8 V
 VDD  3.6 V
1.3
1.3
1.3
s



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