CS4220 datasheet(8/32 Pages) CIRRUS

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CS4220 CS4221

DS284PP3

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4221)

(TA = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 30 pF)

Notes: 11. Not tested but guaranteed by design.

12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

13. Data must be held for sufficient time to bridge the transition time of CCLK.

14. For FSCK < 1 MHz.

Parameter

Symbol

Min

Max

Unit

SPI Mode (SPI/I2C = 0)

CCLK Clock Frequency

fsck

-6

MHz

RST rising edge to CS falling

(Note 11)

tsrs

µs

CCLK edge to CS falling

(Note 12)

tspi

500

CS High Time between transmissions

tcsh

1.0

µs

CS falling to CCLK edge

tcss

CCLK Low Time

tscl

CCLK High Time

tsch

CDIN to CCLK rising setup time

tdsu

CCLK rising to DATA hold time

(Note 13)

tdh

Rise time of CCLK and CDIN

(Note 14)

tr2

-100

Fall time of CCLK and CDIN

(Note 14)

tf2

-100

t r2

t f2

t dsu t dh

t sch

t scl

CCLK

CDIN

tcss

t csh

t spi

t srs

RST

Figure 2. SPI Control Port Timing

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