CS4630 datasheet(13/38 Pages) CIRRUS

13 / 38 page

CS4630

DS445PP1

allowing the addition of new or upgraded function-

ality through software updates.

The CS4630 provides an extremely efficient bus

mastering interface to the PCI bus. The PCI Inter-

face function allows economical burst mode trans-

fers of audio data between host system memory

buffers and the CS4630 device. Program code and

parameter data are also transferred to the CS4630

over the PCI interface.

The DMA Engine provides dedicated hardware to

manage transfer of up to 128 concurrent audio/data

streams to and from host memory buffers. The

DMA Engine provides hardware scatter-gather

support, allowing simple buffer allocation and

management. This implementation improves sys-

tem efficiency by minimizing the number of host

interrupts.

The CS4630 supports a variety of audio I/O config-

urations including a single CS4297/97A/98/99

CrystalClear

AC ’97

Codec

dual

CS4297/97A/98/99 codecs where the second codec

is used to support 4-Channel audio or resides in a

portable’s docking station. The system’s flexibility

is further enhanced by the inclusion of a bi-direc-

tional serial MIDI port, a joystick port, a hardware

volume control interface, a ZV Port interface, and

a serial data port which allows connection of an op-

tional external EEPROM device.

2.1

Stream Processor DSP Core

The CS4630 Stream Processor (SP) is a custom

DSP core design which is optimized for processing

and synthesizing digital audio data streams. The SP

features a Somewhat Long Instruction Multiple

Data (SLIMD) modified dual Harvard architecture.

The device uses a 40-bit instruction word and oper-

ates on 32-bit data words. The SP includes two

Multiply-Accumulate (MAC) blocks and one 16-

bit Arithmetic and Logic Unit (ALU). The SP core

is conservatively rated at 420 Million Instructions

per second (420 MIPS) when running at an 140

MHz internal clock speed. The MAC units perform

dual 20-bit by 16-bit multiplies and have 40-bit ac-

cumulators, providing higher quality than typical

16-bit DSP architectures.

A programmable Phase Locked Loop (PLL) circuit

generates the high frequency internal SP clock

from a lower frequency input clock. The input to

the PLL may be from a crystal oscillator circuit or

the serial port clock ABITCLK/SCLK. Clock con-

trol circuitry allows gating of clocks to various in-

ternal functional blocks to conserve power during

power conservation modes, as well as during nor-

mal modes of operation when no tasks are being

executed.

2.2

Legacy Support

Legacy games are supported by CrystalClear Leg-

acy Support (CCLS), DDMA, or PC/PCI interface.

In both motherboard and add-in card designs,

CCLS and DDMA provide support for legacy

games by providing a hardware interface that sup-

ports a Sound Blaster Pro™ compatible interface, as

well as support for FM, MPU-401, and joystick in-

terfaces. These hardware interfaces provide PCI-

only games compatibility for real-mode DOS and

Windows DOS box support.

For motherboard designs, PC/PCI can be used by

connecting the PCGNT# and PCREQ# pins to the

appropriate pins on the south bridge motherboard

chip. The PC/PCI interface is compliant with In-

tel’s PC/PCI spec. (version 1.2). The BIOS must

enable the PC/PCI mechanism at boot time on both

the CS4630 and the south bridge.

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