DS80C400 datasheet(33/97 Pages) DALLAS

33 / 97 page

DS80C400 Network Microcontroller

33 of 97

configuration through an SFR interface, manages all Tx/Rx packet activity and status reporting through an on-chip

8kB SRAM. To further reduce host (DS80C400) software intervention, the MAC can be set up to generate a

hardware interrupt following each transmit or receive status report. The DS80C400 MAC can be operated in half-

duplex or full-duplex mode with flow control, and provides multicast/broadcast-address filtering modes as well as

VLAN tag-recognition capability.

The DS80C400 features a full-function CAN 2.0B controller. This controller provides 15 total message centers, 14

of which can be configured as either transmit or receive buffers and one that can serve as a receive double buffer.

The device supports standard 11-bit or 29-extended message identifiers, and offers two separate 8-bit media

masks and media arbitration fields to support the use of higher-level CAN protocols such as DeviceNet and SDS. A

special auto-baud mode allows the CAN controller to quickly determine required bus timing when inserted into a

new network. A SIESTA sleep mode has been made available for times when the CAN controller can be placed

into a power-saving mode.

The DS80C400 has resources that far exceed those normally provided on a standard 8-bit microcontroller. Many

functions, which might exist as peripheral circuits to a microcontroller, have been integrated into the DS80C400.

Some of the integrated functions of the DS80C400 include 16 interrupt sources (six external), four timer/counters, a

programmable watchdog timer, a programmable IrDA output clock, an oscillator-fail detection circuit, and an

internal 2X/4X clock multiplier. This frequency multiplier allows the microcontroller to operate at full speed with a

reduced crystal frequency, reducing EMI.

Advanced power-management support positions the DS80C400 for portable and power-conscious applications.

The low-voltage microcontroller core runs from a 1.8V supply while the I/O remains 5V tolerant, operating from a

3.3V supply. A power-management mode (PMM) allows software to switch from the standard machine cycle rate of

4 clocks per cycle to 1024 clocks per cycle. For example, 40MHz standard operation has a machine cycle rate of

10MHz. In PMM, at the same external clock speed, software can select a 39kHz machine cycle rate, considerably

reducing power consumption. The microcontroller can be configured to automatically switch back from PMM to the

faster mode in response to external interrupts or serial port activity. The DS80C400 provides the ability to place the

CPU into an idle state or an ultra-low-power stop-mode state. As protection against brownout and power-fail

conditions, the microcontroller is capable of issuing an early warning power-fail interrupt and can generate a power-

fail reset.

Defaulting to true 8051-memory compatibility (when the ROM is disabled), the microcontroller is most powerful

when taking advantage of its enhanced memory architecture. The DS80C400 has a selectable 10-bit stack pointer

that can address up to 1kB of on-chip SRAM stack space for increased code efficiency. It can be operated in a 24-

bit paged or 24-bit contiguous address mode, giving access to a much larger address range than the standard 16-

bit address mode. Support for merged program and data memory access allows in-system programming, and it can

be configured to internally demultiplex data and the lowest address byte, thereby eliminating the need for an

external latch and potentially allowing the use of slower memory devices.

80C32 COMPATIBILITY

The DS80C400 is a CMOS 80C32-compatible microcontroller designed for high performance. Every effort has

been made to keep the core device familiar to 80C32 users while adding many enhanced features. The DS80C400

provides the same timer/counter resources, full duplex serial port, 256 Bytes of scratchpad RAM, and I/O ports as

the standard 80C32. Timers default to 12 oscillator clocks per tick operation to keep timing compatible with original

8051 systems. New hardware functions are accessed using special function registers (SFRs) that do not overlap

with standard 80C32 locations. All instructions perform exactly the same functions as their 8051 counterparts. Their

effect on bits, flags, and other status functions is identical. Because the device runs the standard 8051 instruction

set, in general, software written for existing 80C32-based systems work on the DS80C400. The primary exceptions

are related to timing-critical issues, since the high-performance core of the microcontroller executes instructions

much faster than the original, both in absolute and relative number of clocks.

The relative time of two DS80C400 instructions might differ from the traditional 8051. For example, in the original

architecture the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction required the same amount

of time: two machine cycles or 24 oscillator cycles. In its default configuration (machine cycle = 4 oscillator cycles),

the DS80C400 executes the “MOVX A, @DPTR” instruction in as little as two machine cycles or 8 oscillator cycles,

but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their

original counterparts, they now have different execution times. Examine the timing of each instruction for familiarity

DS80C400 Datasheet(PDF) 33 Page - Dallas Semiconductor

DS80C400 Datasheet(HTML) 33 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

Datasheet Download

Link URL