DS80C400 datasheet(49/97 Pages) DALLAS

49 / 97 page

DS80C400 Network Microcontroller

49 of 97

40-Bit Accumulator

The accelerator also incorporates an automatic accumulator function, permitting the implementation of multiply-

and-accumulate and divide-and-accumulate functions without any additional delay. Each time the accelerator is

used for a multiply or divide operation, the result is transparently added to a 40-bit accumulator. This can greatly

increase speed of DSP and other high-level math operations.

The accumulator can be accessed any time the multiply/accumulate status flag (MCNT1;D2h) is cleared. The

accumulator is initialized by performing five writes to the multiplier C register (MC;D5h), LSB first. The 40-bit

accumulator can be read by performing five reads of the multiplier C register, MSB first.

Ethernet Controller

The DS80C400 incorporates a 10/100Mbps Ethernet controller, which supports the protocol requirements for

operating an Ethernet/IEEE 802.3-compliant PHY device. It provides receive, transmit, and flow control

mechanisms through a media-independent interface (MII), which includes a serial management bus for configuring

external PHY devices. The MII can be configured to operate in half-duplex or full-duplex mode at either 10Mbps or

100Mbps, or can support 10Mbps ENDEC mode operation.

For half-duplex mode operation, the DS80C400 shares the Ethernet physical media with other stations on the

network. The DS80C400 follows the IEEE 802.3 carrier-sense multiple-access with collision detection (CSMA/CD)

method for accessing the physical media. The MAC waits until the physical carrier is idle before attempting a

transmission. Having multiple stations on the network results in the possibility of transmissions from different

stations colliding. When a collision is detected, the MAC waits some number of time slots (according to an internal

back-off timer) before attempting retransmission. Unless instructed otherwise, the MAC automatically attempts to

retransmit collided frames up to 16 times before aborting the transmit frame. As a means of flow control when

receiving data, the MAC uses a back-pressure scheme, transmitting a jamming signal to force collisions on

incoming frames transmitted by other stations. Using this back-pressure scheme gives the DS80C400 control of

the network or time to free up needed receive data buffers.

For full-duplex mode operation, the physical media connects the DS80C400 directly to only one other station,

allowing simultaneous transmit and receive activity between the two without risk of collision. Hence, no media-

access method (i.e., CSMA/CD) needs to be used. For full-duplex operation, the flow control mechanism is the

PAUSE control frame. When needing time to free additional receive data buffers, the DS80C400 can initiate a

PAUSE control frame, requesting that the other station suspend transmission attempts for a specified number of

time slots.

Figure 2. Ethernet Controller Block Diagram

MII MANAGEMENT

BLOCK

<SERIAL

INTERFACE BUS TO

EXTERNAL PHY(s)>

MII I/O BLOCK

(TRANSMIT,

RECEIVE, AND

FLOW CONTROL)

CSR REGISTERS

ADDRESS CHECK

BLOCK

POWER MANAGEMENT

BLOCK

BCU

Tx/Rx BUFFER

MEMORY

(8kB)

EXTERNAL

PHY(s)

DS80C400 ON-CHIP ETHERNET CONTROLLER

DS80C400

CPU

NOTE: WHEN CONNECTING THE DS80C400 TO AN EXTERNAL PHY, DO NOT CONNECT THE

RSTOL TO THE RESET OF THE PHY. DOING SO MAY

DISABLE THE ETHERNET TRANSMIT.

DS80C400 Datasheet(PDF) 49 Page - Dallas Semiconductor

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