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AS3911B Datasheet(PDF) 43 Page - ams AG |
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AS3911B Datasheet(HTML) 43 Page - ams AG |
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43 / 155 page ![]() ams Datasheet: 2014-Jun-12 [v1-08] AS3911B – 43 Appl icatio n I n f o rm a t i o n Figure 27: SPI Communication: Loading of FIFO Reading Received Data from FIFO Reading received data from the FIFO is similar to reading data from an addressable registers. Difference is that in case of reading more bytes they all come from the FIFO. SPI operation mode bits 10 indicate FIFO operations. In case of reading the received data from the FIFO all bits <C5 – C0> are set to 1. On the following SCLK rising edges the data from FIFO appears as in case of read data from addressable registers. In case the command is terminated by putting /SS high before a packet of 8 bits composing one byte is read that particular byte is considered unread and will be the first one read in next FIFO read operation. Figure 28: SPI Communication: Reading of FIFO 1 0 0 0 000 0 1 to 96 bytes X SCLK rising edge Data is transfered from µC SCLK falling edge Data is sampled 10 pattern indicates FIFO mode X Start of payload Data /SS SCLK MOSI /S S SC LK MOS I MIS O 10 1 1 1 1 1 1 1 to 96 bytes X tristate tristate X S C LK rising edge D ata is transfered from µ C S C LK falling edge D ata is sam pled 10 pattern indicates FIFO m ode SC LK rising edge D ata is m oved from FIFO SC LK falling edge D ata is transfered to µC |
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