HT9480 datasheet(22/57 Pages) HOLTEK

22 / 57 page

Display memory

LCD display

The LCD display memory is embedded in the

data memory (mapped to the addresses

C0H~E2H of bank 27). It can be read and writ-

ten to as a normal data memory. The following

figure illustrates the mapping between the dis-

play memory and the LCD pattern.

To turn the display on/off, the programmer

writes 1 or 0 to the corresponding bit of the

display memory. The LCD display module can

be of any form as long as the number of the

common doesn’t exceed 4 and the number of the

segment is not over 35.

The entire number of the LCD driver output is

×4. The LCD driver can directly drive an LCD

of 1/4 duty cycle and 1/3 bias. All of the LCD

segments are random at the initial clear mode.

The frequency of the LCD driving clock is fixed

at about 256Hz, and cannot be changed. It is set

by HOLTEK according to the application.

The following is an example of an 8-segment

digit display, which shows a waveform of “5”.

Pager decoder

The pager decoder is a POCSAG code pager

decoder at 512, 1200, or 2400 bps data rate,

compatible with CCIR radio paging Code No.1

(POCSAG Code). The decoder supports six user

addresses and six independently programma-

ble user frames.

HT9480

23th Feb ’98

HT9480 Datasheet(PDF) 22 Page - Holtek Semiconductor Inc