HT9580 datasheet(29/63 Pages) HOLTEK

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SPI configure register

Address

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

State on

POR

0032H

SPI-CONFIG

S/M

LEN1

LEN0

REQST

SPIFG

CLK_EDG

SPI_EN

START

0111 1000

HT9580

April 28, 2000

Preliminary

· S/M: Slave/master mode selection

When S/M is "0", HT9580 is in the master

mode. Otherwise, HT9580 is in the slave

mode.

S/M

Master mode

(SCK is output)

Slave mode

(SCK is input)

· LEN0, LEN1: Data length

The LEN0 and LEN1 will determine the data

length between exchange.

LEN1

LEN0

Data Length (Bit)

· REQST: SPI request (read only)

When FLEXTM decoder wants to exchange

data with HT9580, the REQST will have low

pulse.

· SPIFG: SPI complete flag

0 (clear): Data transfer to external device has

been completed.

1 (set): No valid completion of data transfer.

The bit is cleared by hardware and set

by software.

· CLK_EDG: Data sampling edge

The CLK_EDG will determine the valid

MISO and MOSI sampling edge of SCK clock.

CLK_EDG Rising edge

Falling edge

· SPI_EN: The SPI enable

SPI_EN

When the SPI cir-

cuit is disabled, the

POCSAG decoder

I/O pins will be en-

abled

The SPI cir-

cuit and SPI

I/O pins will

be enabled

· START: The data exchange start or not

START

No data exchange

Data

exchange

start

When the bit is set by software, the SPI data

exchange will start. After the first bit data ex-

change is completed, the START bit will clear

to low again by hardware.

HT9580 Datasheet(PDF) 29 Page - Holtek Semiconductor Inc

HT9580 Datasheet(HTML) 29 Page - Holtek Semiconductor Inc

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