HT9580 datasheet(36/63 Pages) HOLTEK

36 / 63 page

HT9580

April 28, 2000

Preliminary

The decoder control address (0019H) contains a

battery low flag (BL), an out of range flag (OR),

decoder standby flag (STB), a decoder software

reset (RES), and a decoder on/off control bit

(ON). The data ready and battery fail flag are in

the interrupt flag register (0006H). It not only

records the status information but controls the

operation of the decoder.

If the flag status of the battery fail (BF_FG)

changes from ²0² to ²1², the following condi-

tions occur.

The pager controller generates an interrupt

if the value of the data ready interrupt is ²0².

The pager controller does not generate any

interrupt and no data is transmitted to it if

the value of the data ready interrupt is ²1².

On the other hand, if the status of the battery

fail flag (BF_FG) changes from ²1² to ²0², the

internal node PA.7 of the pager controller will

supply a wake-up function. After the decoder

asserts the data ready request, the data ready

interrupt is generated and the DR_FG bit (bit

5 of 0006H) is set high; then the data ready in-

terrupt subroutine runs to process the call

data on the message buffer and resets the

DR_FG bit low.

The functional bits (ON, RES) and indication

bits ( STB, OR,BL, BF_FG and DR_FG) are

all used to control the status of the decoder

which is operated through the pager control

address as described in the following table.

INT flag register (0006H)

Symbol

Bit

R/W

Description

BF_FG

Battery fail indication bit

Once the decoder detects that the battery fail condition occurred,

the BF_FG will go high.

DR_FG

R/W

Data ready interrupt indication bit

When a valid call is detected, data transfers to the message

buffer. The DR_FG bit goes high when the message is terminated

within 46 bytes, one batch is at the end during the message receiv-

ing or the data buffer is full if the data length is more than 46

bytes. The mC software should read the data on the message

buffer within one POCSAG message codeword (32-bit) time. The

mC software has to clear the DR_FG bit low.

Decoder control register (0019H)

Symbol

Bit

R/W

Description

R/W

On/Off control bit

This bit selects the ON or STANDBY state of the decoder

0: ON state

1: STANDBY RES

If SPI circuit is enabled, it would be better if this bit is set high to

reduce power consumption.

RES

R/W

Resets the decoder core output

The mC has to set the RES bit low and then high after the pager

controller is turned on.

The reset status must be released before writing data to the de-

coder configuration RAM.

HT9580 Datasheet(PDF) 36 Page - Holtek Semiconductor Inc

HT9580 Datasheet(HTML) 36 Page - Holtek Semiconductor Inc

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