TP87C51FC datasheet(9/18 Pages) INTEL

9 / 18 page

AUTOMOTIVE 87C51FAFBFCFC-20

NOTES

1 Capacitive loading on Ports 0 and 2 may cause noise pulses above 04V to be superimposed on the VOLs of ALE and

Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins

change from 1 to 0 In applications where capacitive loading exceeds 100 pF the noise pulses on these signals may exceed

08V It may be desirable to qualify ALE or other signals with Schmitt triggers or CMOS-level input logic

2 Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 09 VCC specification when the

address lines are stabilizing

3 See Figures 6 – 9 for test conditions Minimum VCC for Power Down is 2V

4 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and

5 Under steady state (non-transient) conditions IOL must be externally limited as follows

Maximum IOL per port pin

10mA

Maximum IOL per 8-bit port

Port 0

26 mA

Ports 1 2 and 3

15 mA

Maximum total IOL for all output pins

71 mA

If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater

than the listed test conditions

270961 – 7

ICC Max at other frequencies is given by

Active Mode

ICC Max e (125 c Osc Freq) a 15

Idle Mode

ICC Max e (05 c Osc Freq) a 4

Where Osc Freq is in MHz ICC is in mA

Figure 6 ICC vs Frequency

All other pins disconnected

270961 – 8

TCLCH e TCHCL e 5ns

Figure 7 ICC Test Condition Active Mode

All other pins disconnected

270961 – 9

TCLCH e TCHCL e 5ns

Figure 8 ICC Test Condition Idle Mode

All other pins disconnected

270961 – 10

Figure 9 ICC Test Condition Power Down Mode

VCC e 20V to 55V

270961 – 11

Figure 10 Clock Signal Waveform for ICC Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns

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