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CS80C88 Datasheet(PDF) 20 Page - Intersil Corporation

Part # CS80C88
Description  CMOS 8/16-Bit Microprocessor
PDF  32 Pages
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CS80C88 Datasheet(HTML) 20 Page - Intersil Corporation

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3-20
AC Electrical Specifications
VCC = 5.0V ±10%; TA = 0
oC to +70oC (C80C88, C80C88-2)
VCC = 5.0V ±10%; TA = -40
oC to +85oC (I80C88, I80C88-2)
VCC = 5.0V ±10%; TA = -55
oC to +125oC (M80C88)
VCC = 5.0V ±5%;
TA = -55
oC to +125oC (M80C88-2)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
SYMBOL
PARAMETER
80C88
80C88-2
UNITS
TEST CONDITIONS
MIN
MAX
MIN
MAX
TIMING REQUIREMENTS
(1)
TCLCL
CLK Cycle Period
200
-
125
-
ns
(2)
TCLCH
CLK Low Time
118
-
68
-
ns
(3)
TCHCL
CLK High Time
69
-
44
-
ns
(4)
TCH1CH2
CLK Rise Time
-
10
-
10
ns
From 1.0V to 3.5V
(5)
TCL2CL1
CLK Fall Time
-
10
-
10
ns
From 3.5V to 1.0V
(6)
TDVCL
Data in Setup Time
30
-
20
-
ns
(7)
TCLDX1
Data In Hold Time
10
-
10
-
ns
(8)
TR1VCL
RDY Setup Time into 82C84
(Notes 13, 14)
35
-
35
-
ns
(9)
TCLR1X
RDY Hold Time into 82C84
(Notes 13, 14)
0-0-
ns
(10)
TRYHCH
READY Setup Time into 80C88
118
-
68
-
ns
(11)
TCHRYX
READY Hold Time into 80C88
30
-
20
-
ns
(12)
TRYLCL
READY Inactive to CLK (Note 15)
-8
-
-8
-
ns
(13)
TlNVCH
Setup Time for Recognition (lNTR,
NMl, TEST) (Note 14)
30
-
15
-
ns
(14)
TGVCH
RQ/GT Setup Time
30
-
15
-
ns
(15)
TCHGX
RQ Hold Time into 80C88 (Note 16)
40
TCHCL+
10
30
TCHCL+
10
ns
(16)
TILlH
Input Rise Time (Except CLK)
-
15
-
15
ns
From 0.8V to 2.0V
(17)
TIHIL
Input Fall Time (Except CLK)
-
15
-
15
ns
From 2.0V to 0.8V
TIMING RESPONSES
(18)
TCLML
Command Active Delay (Note 13)
5
35
5
35
ns
CL = 100pF
for all 80C88 outputs
in addition to internal
loads.
(19)
TCLMH
Command Inactive (Note 13)
5
35
5
35
ns
(20)
TRYHSH
READY Active to Status Passive
(Notes 15, 17)
-
110
-
65
ns
(21)
TCHSV
Status Active Delay
10
110
10
60
ns
(22)
TCLSH
Status Inactive Delay (Note 17)
10
130
10
70
ns
(23)
TCLAV
Address Valid Delay
10
110
10
60
ns
(24)
TCLAX
Address Hold Time
10
-
10
-
ns
(25)
TCLAZ
Address Float Delay
TCLAX
80
TCLAX
50
ns
(26)
TCHSZ
Status Float Delay
-
80
-
50
ns
(27)
TSVLH
Status Valid to ALE High (Note 13)
-
20
-
20
ns
(28)
TSVMCH
Status Valid to MCE High (Note 13)
-
30
-
30
ns
(29)
TCLLH
CLK Low to ALE Valid (Note 13)
-
20
-
20
ns
(30)
TCLMCH
CLK Low to MCE High (Note 13)
-
25
-
25
ns
(31)
TCHLL
ALE Inactive Delay (Note 13)
4
18
4
18
ns
80C88



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