3-23

FIGURE 25. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88) (Continued)

NOTES:

22. Signals at 82C84A or 82C86 are shown for reference only.

23. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active

high 82C88 CEN.

24. Status inactive in state just prior to T4.

25. Cascade address is valid between first and second INTA cycles.

26. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is

shown for second INTA cycle.

T1

T2

T3

T4

TW

TCLSH

(SEE NOTE 24)

TCLDX2

TCLDV

TCLAX

TCLMH

(18) TCLML

TCHDTH

(19) TCLMH

TCVNX

TCLAV

TCHSV

TCLSH

CLK

S2, S1, S0 (EXCEPT HALT)

WRITE CYCLE

AD7-AD0

DEN

AMWC OR AIOWC

MWTC OR IOWC

82C88

OUTPUTS

SEE NOTES 22, 23

INTA CYCLE

A15-A8

(SEE NOTES 25, 26)

AD7-AD0

MCE/PDEN

DT/R

INTA

DEN

82C88 OUTPUTS

SEE NOTES 22, 23, 25

RESERVED FOR

CASCADE ADDR

(25) TCLAZ

(28) TSVMCH

(30) TCLMCH

TCVNV

SOFTWARE

HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH

(18) TCLML

TCLMH (19)

TCLDX1 (7)

(18)TCLML

POINTER

INVALID ADDRESS

AD7-AD0

S2, S1, S0

TCHDTL

TCHSV (21)

(34)

(22)

(33)

(24)

DATA

TCVNX (36)

(19)

(6)

TDVCL

TCLMCL

(32)

(41)

(42)

(35)

(36)

(23)

(21)

(22)

TCLAV (23)

TCVNV

(35)

A15-A8

80C88