6

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION

OPEN

GROUND

VDD

9V

± -0.5V

OSCILLATOR

50kHz

25kHz

CD4510BMS

Static Burn-In 1

(Note 1)

2, 6, 7, 11, 14

1, 3-5, 8-10, 12, 13,

15

16

Static Burn-In 2

(Note 1)

2, 6, 7, 11, 14

8

1, 3-5, 9, 10, 12, 13,

15, 16

Dynamic Burn-

In (Note 1)

-

1, 3, 4, 8, 9, 12, 13

10, 16

2, 6, 7, 11, 14

15

5

Irradiation

(Note 2)

2, 6, 7, 11, 14

8

1, 3-5, 9, 10, 12, 13,

15, 16

NOTES:

1. Each pin except VDD and GND will have a series resistor of 10K

± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K

± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,

VDD = 10V

± 0.5V

Logic Diagrams

FIGURE 1. CD4510BMS

P

Q

Q

PE

C

T

P1

*

4

Q1

6

9

RESET

*

P

Q

Q

PE

C

T

P2

*

12

Q2

11

P

Q

Q

PE

C

T

P3

*

13

Q3

14

P

Q

Q

PE

C

T

P4

*

3

Q4

2

PRESET

*

ENABLE

1

15

CLOCK

*

7

CARRY OUT

U/D

Q4

Q3

Q4

U/D

Q2

U/D Q3 U/D

U/D

Q2

Q3

U/D

Q2

Q3

Q3

Q4

Q4

Q4

Q3

Q3

Q2

Q2

Q1

5

CARRY IN

*

10

UP/DOWN

*

Q1

U/D

U/D

VDD

VSS

BY CMOS PROTECTION

NETWORK

U/D

Q4

Q2

Q2

CD4510BMS, CD4516BMS