6-53

PARAMETER

LIMITS

UNITS

CDP1826C

(NOTE 1)

MIN

(NOTE 2)

TYP

MAX

WRITE - CYCLE TIMES (FIGURES 6 AND 7)

Address to TPA Setup, High Byte

100

-

-

ns

Address to TPA Hold

100

-

-

ns

Address Setup, Low Byte

500

250

-

ns

TPA Pulse Width

200

-

-

ns

Chip Select Setup

700

350

-

ns

Write Pulse Width

300

200

-

ns

Write Recovery

100

-

-

ns

Data Setup

400

200

-

ns

Data Hold from End of MWR

100

50

-

ns

Data Hold from End of Chip Select

125

50

-

ns

NOTES:

1. Time required by a limit device to allow tor the indicated function.

A0 - A5

HIGH ORDER

ADDRESS BYTE

LOW ORDER ADDRESS BYTE

VALID CHIP SELECT

HIGH IMPEDANCE

MRD

CS1

• CS2

BUS

VALID DATA

FIGURE 5. TIMING WAVEFORMS FOR READ-CYCLE 2 (TPA HIGH)

CDP1826C