6-47

March 1997

CDP1826C

CMOS 64-Word x 8-Bit

Static RAM

Features

• Ideal for Small, Low-Power RAM Memory Require-

ments in Microprocessor and Microcomputer Applica-

tions

• Interfaces

with

CDP1800-Series

Microprocessors

Without Additional Address Decoding

• Daisy Chain Feature to Further Reduce External

Decoding Needs

• Multiple Chip-Select Inputs for Versatility

• Single Voltage Supply

• No Clock or Precharge Required.

Pinout

CDP1826C (PDIP)

TOP VIEW

Description

The CDP1826C is a general purpose, fully static, 64-word x

8-bit random-access memory, for use in CDP1800-series or

other microprocessor systems where minimum component

count and/or price performance and simplicity in use are

desirable.

The CDP1826C has 8 common data input and data-output

terminals with three-state capability for direct connection to a

standard bidirectional data bus. Two chip-select inputs - CS1

and CS2 - are provided to simplify memory-system expan-

sion. An additional select pin, CS/A5, is provided to enable

the CDP1826C to be selected directly from the CDP1800

multiplexed address bus without additional latching or

decoding. In an 1800 system, the CS/A5 pin can be tied to

any MA address line from the CDP1800 processor. A TPA

input is provided to latch the high-order bit of this address

line as a chip-select for the CDP1826C. If this CS/A5 input is

latched high, and if CS = 1 and CS2 = 0 at the appropriate

time in the memory cycle, the CDP1826C will be enabled for

writing or reading. In a non-1800 system, the TPA pin can be

tied high, and the CS/A5 pin can be used as a normal

address input.

The six input-address buffers are gated with the chip-select

function to reduce standby current when the device is dese-

lected, as well as to provide for a simplified power down

mode by reducing address buffer sensitivity to long fall times

from address drivers which are being powered down.

Two memory control signals, MRD and MWR, are provided

for reading from the writing to the CDP1826C. The logic is

designed so that MWR overrides MRD, allowing the chip to

be controlled from a single R/W.

A CHIP ENABLE OUTPUT is provided for daisy-chaining to

additional memories or I/O devices. This output is high

whenever the chip-select function selects the CDP1826C,

which deselects any other chip which has its CS input con-

nected to the CDP1826C CEO output. The connected chip is

selected when the CDP1826C is deselected and the MRD

input is low. Thus, the CEO is only active for a read cycle

and can be setup so that a CEO of another device can feed

the MRD of the CDP1826C, which in turn selects a third chip

in the daisy chain.

The CDP1826C has a recommended operating voltage of

4.5V to 5.5V and is supplied in 22 lead dual-in-line plastic

packages (E suffix). The CDP1826C is also available in chip

form (H suffix).

Ordering Information

PACKAGE

TEMP. RANGE

PART NUMBER

PKG.

NO.

PDIP

CDP1826CE

E22.4

1

11

10

9

8

7

6

5

3

2

4

22

12

13

14

15

16

17

18

19

21

20

BUS 1

BUS 2

BUS 3

BUS 4

BUS 5

BUS 6

CS1

BUS 7

CS2

A0

A1

A2

A3

CS/A5

A4

TPA

MRD

MWR

CEO

BUS 0

File Number

1311.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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