ADC built-in self-test algorithms

AN4371

10/29

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ADC built-in self-test algorithms

ADC contains three self test algorithms in order to test its functionality.

The SPC56xx uses two types of parameter settings to define the ADC self-test operation:

•

Sample phase duration settings programmed into the INPSAMP_S, INPSAMP_RC,

and INPSAMP_C fields of the Self-Test Configuration Register (STCR1).

•

Threshold values for analog watchdog algorithms

In order to support different loading and switching times, several different conversion timing

registers (CTR) are present. There is one register per channel type.

Table 2 represents the typical values for INPSAMP_x register. For detailed description of

INPSAMP_x calculation please refer to the Reference Manual.

Recommended setting for INPSAMP_S is the maximum value of this register field due to

slow sample capacitor settling time at low temperature for S0 algorithm.

2.1

Self-test execution flow

The number of channels converted at the end of each chain is 1 (except for Algorithm S, in

which all the steps are performed at once without any functional conversion interleaved). In

Scan Mode, consecutive steps of selected self test algorithm are converted continuously at

the end of each chain of normal conversions.

Table 3. Sampling phase duration for the test conversions

INPSAMP_C

Sampling phase duration for the test conversions related to the algorithm C. Valid

self-test values for this field are given below.

Minimum: 0x18

Maximum: 0xFF

INPSAMP_RC

Sampling phase duration for the test conversions related to the algorithm RC.

Valid self-test values for this field are given below.

Minimum: 0x60

Maximum: 0xFF

INPSAMP_S

Sampling phase duration for the test conversions related to the algorithm S. Valid

self-test values for this field are given below.

Minimum: 0xFF

Maximum: 0xFF

Table 4. Sample phase settings

Register field

Recommended setting

INPSAMP_C

0x18h

INPSAMP_RC

0x60h

INPSAMP_S

0xFFh