Space-grade description

TN0873

4/11

DocID022757 Rev 4

1.4.4

Wafer qualification

Wafers eligible for the ST space-grade level (see Section 1.1) are screened as described in

Table 2. Only wafers that have been successfully screened can be used to produce dice of

the ST space-grade level.

Table 2. Space-grade level

Step #

Step definition

Conditions

Acceptance

Acceptance

level n = 38(1)

1

According to the ST qualified PID as

applicable

(3)

(3)

2

n samples

3

Electrical test read and record

at 25 °C

As per ESCC detail specification (DC/AC

parameters for ICs or DC for discrete)

A3/R4(5)

4

Electrical test read and record

As per ESCC detail specification (DC

parameters)

5

Electrical test read and record

at 25 °C for drift parameters

As per ESCC detail specification drift

table

-/-

-/-

6

High temperature reverse

bias(6)

As per ESCC detail specification

conditions

-/-

-/-

7

Electrical test read and record

at 25°C for drift parameters(6)

As per ESCC detail specification drift

table

A1/R2

A2/R3

8

Burn-in (240 hrs)

As per ESCC detail specification

conditions

-/-

-/-

9

Electrical test read and record

at 25° C for drift parameters

As per ESCC detail specification drift

table

A1/R2

A2/R3

10

Electrical test read and record

at 25 °C

As per ESCC detail specification (DC/AC

parameters or DC for discrete)

A2/R3

A3/R4

11

Electrical test read and record

at -55 °C/+125 °C

As per ESCC detail specification (DC

parameters)

12

Life test 1000 hrs

As per ESCC detail specification

conditions

-/-

-/-

13

Electrical test read and record

at 25 °C

As per ESCC detail specification end-

point electrical measurements

A0/R1

A0/R1

14

Check for lot failure

Check from step 3 to step 11

A2/R3

A3/R4

1. Ax/Ry: accepted if x rejects or less / refused if y rejects or more.

2. According to applicable ESCC 5000 or ESCC 9000 (chart F2 and F3 up to PIND test).

3. The number of samples allows the qualification of up to 3 wafers, therefore limiting the maximum quantity of the product in

die form per line item to: 1000 dice maximum per line item for the 54HCMOS/CMOS4000B and diodes, and 5000 dice

maximum per line item for bipolar transistors. The number of samples can be increased in the Premium option. Contact ST

for the corresponding acceptance level.

4. Sample size and acceptance criteria are based on the ECSS-Q-ST-60-05C specification, with limited sample size to 25 and

38 pieces. Data provided are for the default 25 samples.

5. Electrical rejects are not counted as failures if due to the ST assembly process.

6. Electrical tests at high/low temp and/or HTRB are optional and shall be done only on customer request and specified on the

purchase order at additional cost.