AN2511 datasheet(6/43 Pages) STMICROELECTRONICS

6 / 43 page

PMBus introduction

AN2511

6/43

Doc ID 13286 Rev 2

PMBus introduction

1.1

PMBus protocol description

The PMBus protocol is intended to cover a wide range of power system architectures and

converters.

PMBus devices must use the system management bus (SMBus), version 1.1. Implemented

over the industry-standard SMBus serial interface, the PMBus protocol facilitates the

programming, control and real-time monitoring of compliant power conversion products.

1.1.1

SMBus version 1.1

The system management bus (SMBus) is a two-wire interface through which various system

component chips can communicate with each other and with the rest of the system. It is

based on the principles of operation of I2C.

For more information about SMBus, refer to AN1713, available from www.st.com.

1.1.2

Extensions to SMBus version 1.1 specification

Block write-block-read process call

To support certain commands of the PMBus command language, PMBus devices must

support the "Block write-block-read process call" described in Section 5.5.8 of Version

2.0 of the SMBus Specification.

Host notify protocol

PMBus devices may support the host notify protocol described in Section 5.5.9 of

Version 2.0 of the SMBus Specification. If a PMBus device supports the host notify

protocol, the two data bytes sent to the host are the same as the data bytes returned by

the STATUS_WORD command.

Group command protocol

PMBus devices must support the group command protocol. The group command

protocol is used to send commands to more than one PMBus device. The commands

are received in one transmission. When the devices detect the STOP condition that

ends the command, they all begin executing the command they received.

Addressing

PMBus devices use seven bit addresses.

Packet error checking (PEC)

Support for the SMBus packet error checking (PEC) protocol is optional.

1.2

Hardwired signals

1.2.1

Electrical interface

The following diagram shows the interface between different PMBus devices. ST72264G1 is

the selected microcontroller, which has a multi-master I2C interface. This microcontroller

acts as PMBus master. It communicates with any compatible PMBus slave using a 4-pin

interface. SMBC is the clock from the master. SMBD is the data pin. Both SMBC and SMBD

should be pulled up with a 4.7 k

Ω resistor. SMBALERT is the SMBus alert pin, which helps

AN2511 Datasheet(PDF) 6 Page - STMicroelectronics

AN2511 Datasheet(HTML) 6 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datasheet Download

Link URL