July 2009

Doc ID 15110 Rev 1

1/22

AN2842

Application note

Paralleling of power MOSFETs in PFC topology

Introduction

The current handling capability demands on power supply systems to meet high load

current requirements and provide greater margins for overload and reliability, often exceed

the capability of the largest semiconductor devices considered, and their paralleling may

become an attractive alternative. All semiconductor circuits using parallel connected devices

to switch to higher load currents can easily be analyzed by using Kirchoff's law. As long as

all voltage drops in the parallel branches are equal, the currents through the branches are of

similar values if the resistance in each branch is the same. This is logical, but when we

consider the various functions where switching devices are employed, we must also

consider the parameters of each single switching device and all the parasitic phenomena

related to the device.

In this paper we review several factors that influence the behaviors of devices in parallel

configurations. When devices operate in parallel configurations to provide a good dynamic

equilibrium among device currents, consideration should be given to current sharing. The

layout design must be carried out carefully to minimize the differences between device

branches. In addition, switching parameters of devices may not be the same, causing one to

be continuously stressed (by at some time supporting all the input current). Naturally, this

problem worsens as the number of paralleled devices increases. Therefore, it is very

important to understand which factors are linked to the device that cause current imbalance.

Concerning power MOSFET devices, there are many parameters that can influence the

current imbalance and in principle they can be summarized as threshold voltage, gain,

intrinsic capacitances, ON resistance and working temperature mismatches. Individually or

in combination, mismatch between these parameters may produce serious imbalances and

could cause device failure.

In order to investigate the impact of the different factors, some PFC topologies have been

analyzed. The study has included different topologies to understand if the device behaviors

are also related to the configuration. In this paper, three booster PFC topologies are

discussed. In the first topology, a booster PFC is developed using two power MOSFETs

connected directly in parallel (

Figure 1). In this case, two different drive circuits are used for

each single device. Another topology under analysis uses two PFC blocks connected in

parallel (

Figure 2). Also in this case, two drive circuits pilot the gate pin. Finally, a topology

with three devices connected in a parallel configuration is analyzed (

Figure 3).

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