PM0222 datasheet(11/33 Pages) STMICROELECTRONICS

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PM0222

Interrupt management

4.1

Vector table

The Cortex-M0 vector table is fixed at address 0x0000_0000 (see “Cortex-M0 Devices

Generic User Guide”, §2.3.4). At Brain startup, address 0x0000_0000 is located in RAM

Bank 1 and the vector table has been copied from the main Flash into RAM bank 1. When

an interrupt is triggered, the CPU reads the vector table at 0x0000_0000 which should

initially contain a pointer to the user code in Flash.

When needed, the software can write in the vector table located in RAM bank 1 at

0x0000_0000 to dynamically change the IRQ routines.

4.2

Interrupt activation sequence

Safely activating a peripheral interrupt requires the following steps:

–

make sure the interrupt is disabled and cleared on the peripheral side (this

prevents receiving an interrupt due to a previous event) (see Brain reference

manual for each peripheral register map);

–

clear pending requests for this interrupt on the Cortex-M0 side using the NVIC

ICPR register;

–

set the priority using the NVIC IPR0-IPR7 registers;

–

activate on the Cortex-M0 side using the NVIC ISER register;

–

activate on the peripheral side

Note that most peripherals require clearing interrupt requests on the peripheral side when

handling interrupt service requests to prevent triggering continuous interrupts for the same

event.

For more details on the Cortex-M0 exception model, see “ARMv6-M Architecture Reference

Manual”, §B1.5.

For more details on Cortex-M0 NVIC behavior and registers, see “ARMv6-M Architecture

Reference Manual”, §B3.4.

PM0222 Datasheet(PDF) 11 Page - STMicroelectronics