PM0222 datasheet(19/33 Pages) STMICROELECTRONICS

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PM0222

ECC RAM

7.1

Initialization

To avoid any unexpected ECC error detection, it is mandatory to initialize ECC RAM bank 0

before any read from it. To summarize, the rule is that any data in RAM bank 0 must be

written to before performing the first read.

If full main Flash is copied inside RAM bank 0 and the code execution in RAM is switched,

then no additional sequence is required.

If the application is not suited to the rule, an initialization sequence must be performed. An

easy method would be to fill the full RAM bank 0 with a fixed pattern (all bits to ‘0’ for

instance) before using it.

While executed in main Flash, the customer application must not use RAM bank 0 as a data

area that could be read from before a write is performed (heap / variables area, etc.)

7.2

ECC RAM actions

If a single error is detected on a read access, the ECC mechanism:

–

Generates an interrupt (position 10 in the NVIC).

–

Puts on the bus a corrected version of the data to be read. However, data is not

corrected inside the RAM and needs to be re-written by the user.

–

Provides status information available in the CRMU_ECCR0 register (it indicates

which address generated the error and which bit position in the data is corrupt).

For more details, see Brain reference manual, CRMU registers chapter,

CRMU_ECCR0 description.

Note:

This status register (CRMU_ECCR0) is cleared when read so take care to save the full

information of the read.

If a double error is detected on a read, the ECC mechanism:

–

Generates a reset

–

Puts 0xDEAD_DEAD on the data bus

–

After reset, CRMU_REASON_RESET indicates that ECC is responsible for the

reset and the CRMU_ECCR0 register indicates which RAM address generated

the error and which bits in the words were corrupted. For more details, see Brain

reference manual, CRMU registers chapter, CRMU_REASON_RESET and

CRMU_ECCR0 descriptions.

Note:

The CRMU_ECCR0 register is not reset by the ECC reset, so the status is still available

after reset.

Note:

The CRMU_ECCR0 register is cleared when read, so take care to save the full information

of the read.

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