PM0222 datasheet(20/33 Pages) STMICROELECTRONICS

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Timers

PM0222

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Timers

8.1

Dual timers

All dual-timer registers are described in a structure defined in the Brain header file (.h)

provided by STMicroelectronics.

Brain has eight SP804 dual-timers available at the following addresses in the memory map:



DUALTIMER0 APB base address: 0xA640_0000



DUALTIMER1 APB base address: 0xA740_0000



DUALTIMER2 APB base address: 0xA840_0000



DUALTIMER3 APB base address: 0xA940_0000



DUALTIMER4 APB base address: 0xA680_0000



DUALTIMER5 APB base address: 0xA780_0000



DUALTIMER6 APB base address: 0xA880_0000



DUALTIMER7 APB base address: 0xA980_0000

Dual-timers 0 to 3 are clocked by a clock synchronous to the processor clock. Dual-timers 4

to 7 are clocked by the RC 32 kHz resynchronized on the system clock.

Note:

When the processor clock is lower than or equal to 32 kHz, dual-timers 4 to 7 are not

functional.

Each dual-timer has two timers referred to as “Timer1” and “Timer2” (or A and B in the

interrupt vector table in the Brain reference manual). This section provides a short overview

on the use of a dual-timer. In the following examples Timer1 of dual-timer0 is used to run in

a periodic/one-shot mode and send an interrupt when the timer reaches zero.

Before using these examples dual-timer0 clock has to be enabled in the CRMU (see

Section 3.1: Peripheral clock gating) and the processor clock has to be properly configured

(see Section 3.2: CPU clock configuration) according to the user’s program specifications.

The specific interrupt for dual-timer0 has to be enabled on the Cortex-M0 side (see

Section 4: Interrupt management).

8.1.1

Periodic mode

// disable the timer1 of dual-timer0, and all previous configurations in case of a

// previous use.

DUALTIMER0->Timer1Control = 0x00;

DUALTIMER0->Timer1Load = 0x800000; // load a new timer value.

Then to launch the timer, the Timer1Control register has to be configured. In this example

the timer1 configuration is:



32-bit mode



No division on timer1 incoming clock



Interrupt is enabled for timer1



Periodic mode and timer1 are enabled.

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