AN413 datasheet(8/45 Pages) STMICROELECTRONICS

8 / 45 page

ST9 basic system configuration

AN413

8/45

Doc ID 1875 Rev 2

for external I/O, plus any alternative function assignments of port pins, and internal

interconnections. Table 5,Appendix A, lists the complete set of Port Configuration registers

together with their addresses.

Example:

C7 0A

spp

P3C_PG

F5 FC 05

P3C0R,#00000101b

F5 FD 0F

P3C1R,#00001111b

F5 FE 05

P3C2R,#00000101b

In this example Port 3 pins 4, 5, 6, and 7 are configured as bidirectional pins, with weak pull-

up output and TTL inputs. Pins 0 (T0INA) and 2 (T0INB) are configured as TTL inputs, and

Pins 1 (T0OUTA) and 3 (T0OUTB) are configured as Alternate Function Push-pull outputs.

3.3

Multifunction timer configuration

The ST9 Multifunction Timer is configured by loading suitable control-bit patterns in the

group F page register TCR, TMR, ICR, OACR, and OBCR (see Table 6 in Appendix A). Note

that registers EIMR and CICR provide global control functions common to all on-chip

peripherals and are hence initialized conveniently in the basic system configuration routine.

The External Input Control Register, ICR, controls input source selection (internal/external),

input mode selection (falling/rising edge sensitive, etc.), counter mode of operation

(continuous, one-shot, etc.), and input function (Gate, Trigger, up/down control, etc.).

Example:

F5 FA 54 ld T_ICR,#01010100b

This instruction selects the external input A as a falling-edge-sensitive Trigger input, and the

B input is a normal Port I/O pin.

The Multifunction Timer Control Register, TCR, controls counter clear and prescaler reload

operations as well as providing a counter enable control bit and counter status flags.

Example:

F5 F8 48 ld T_TCR,#01001000b

This instruction halts the counter operation but provides for subsequent UP counting with

counter clear and Prescaler reload on Reg0 or Reg1 capture.

The Multifunction Timer Mode Register, TMR, selects the clock source for the counter-

prescaler input, enables Retrigger or Continuous mode, and controls register load/capture

operations.

Example:

98 8C ld T_TMR,#10001100b

This pattern enables output 1 and disables output 0, disables bi-value modes, and selects

Reg0 for capture and Reg1 for monitor. Retriggerable continuous mode is selected.

The Output Control Register, OACR, links the output T0OUTA to counter overflow/underflow

and Compare events, and provides for subsequent Set, Reset, or Toggle of the external

output. The on-chip event (OCE) may be linked to a COMP0 event.

AN413 Datasheet(PDF) 8 Page - STMicroelectronics

AN413 Datasheet(HTML) 8 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL