AN413 datasheet(10/45 Pages) STMICROELECTRONICS

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ST9 basic system configuration

AN413

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Doc ID 1875 Rev 2

The Interrupt/DMA Control Register, IDCR, is used to set the Interrupt and DMA priority

levels, and the DMA transfer source and destination. It also enables Swap mode and

contains End of Block condition flags.

Example:

F5 F3 D6 ld T0_IDCR,#11000110b

In this example the priority level is set at a value of 6, and the Swap mode is disabled. The

DMA capture channel source is REG0, and the DMA compare channel source is CMP0.

The Interrupt/DMA Mask Register, IDMR, contains a global Multifunction Timer Interrupt

enable plus individual DMA and Interrupt enable bits for overflow as well as successful

capture and comparison events.

Example:

F5 FF 04 ld T_IDMR,#00000100b

0F FF 80 or T_IDMR,#gtien

The first instruction sets the interrupt enable on CMP0, and the second instruction globally

enables all Multifunction Timer interrupts.

The DMA Counter Pointer Register, DCPR, defines the DMA area and source, and specifies

the location of the DMA length register.

Example:

F5 F0 4C ld T0_DCPR,#CPT_LG_DMA

The DMA length register is 4Ch = rr12 = RR76 and the transfer occurs to/from

Program/Data memory.

The DMA Address Pointer Register, DAPR, defines the DMA area and source, and specifies

the location of the DMA address register.

Example:

F5 F1 48 ld T0_DAPR,#CPT_AD_DMA

The DMA address register is 48h = rr8 = RR72. In conjunction with the DPCR value in the

above example it specifies Program memory for the buffer.

3.5

A/D converter configuration/initialization

Configuration of the A/D converter requires loading of 4 registers only, CLR, CRR, ICR, and

IVR (Table 9), and initialization of this device involves, apart from global masking, loading of

two double (threshold registers). Hence a single routine can be written to cover both the

configuration and initialization aspects of A/D Converter use.

The Control Logic Register, CLR, defines the Analog channel conversion start address,

selects internal/ external triggers, and enables continuous or single conversion and power

up/down modes. This register also contains a start/stop status/control bit.

Example:

F5 FD 04 ld AD_CLR,#00000100b

In this example, the conversion scan starts with channel 0 when enabled, powers up the A/D

convertor, halts conversion, and specifies single conversion scan mode.

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