AN413 datasheet(15/45 Pages) STMICROELECTRONICS

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AN413

ST9 basic system configuration

Doc ID 1875 Rev 2

15/45

The specified count value leads to a count period of about 1 millisecond, (3003 x 333ns).

3.9

Timer/watchdog unit initialization

The External Interrupt Priority Level Register, EIPLR, specifies the priority level of four pairs

of external interrupts, a), A1,...D0, D1. It is thus used to set the priority of the

Timer/Watchdog EOC interrupt routine, called via channel A0.

Example:

5C FE ld eiplr,#0FEh

In this example priority levels of 4 and 5 are specified for the pair INTA0, INTA1.

The External Interrupts Pending Bit Register, EIPR, holds the eight interrupt pending bits for

the external interrupts, including, in the present context, the Watchdog/Timer EOC interrupt.

These bits are set by hardware action and reset by software during the service routine.

Example:

90 D3 clr eipr

In this example all the external interrupt pending bits are cleared.

The External Interrupts Mask-Bit Register, EIMR, holds the eight interrupt mask bits for the

external interrupts, including, in the present context, the Timer/Watchdog EOC interrupt.

Example:

4C 01 ld eimr,#ia0

In this example the Timer/Watchdog End of Count on Channel A0 is unmasked.

3.10

Interrupt service routine organization

When an enabled interrupt is acknowledged the Interrupt machine cycle performs the

following actions:

All maskable interrupts are disabled by clearing the EI bit of register CICR.

The PC (two bytes) and the FLAGS register are saved on the System stack.

The PC is loaded with the 16-bit vector stored in the Vector Table.

On exit from the Interrupt service, using an IRET instruction the following operations are

carried out:

The FLAGR register is restored from the System stack.

The PC is restored from the System stack.

The unmasked interrupts are enabled by setting the CICR.EI bit.

In general additional resources must be saved and restored apart from those handled

automatically by the system as listed above. In a typical case these additional resources will

include the two Register pointer registers, the Page-pointer register, and any working

registers used in the Interrupt routine.

An outline for a suitable Interrupt service routine is hence as follows:

Label_int:

work_reg_page0 = (0Dh*2)

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