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ST9 EXTERNAL MEMORY INTERFACE CONFIGURATION

2.2 MODE CONFIGURATION

The various modes of the external memory interface are configured through the bits of the

EMR1 and MODER control registers.

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EMR1 register:

– Mode Control (MC bit 6): by setting this bit, the Intel mode is used for the external memory

interface. In this mode, the ASn pin becomes ALE (Address Load Enable), which corre-

sponds to ASn inverted. The DSn pin becomes OEN (Output Enable), which behaves like

DSn during a Read cycle, but which is forced to 1 during Write cycles. The RWn pin be-

comes WEN (Write Enable), which behaves like DSn during a Write cycle, but which is

forced to 1 during Read cycles.

– Buffer Size (BSZ bit 1): when this bit is 0 (default value), the external memory interface

pins use smaller, less noisy output buffers. This may limit the operation frequency of the

device. Typically, for an internal frequency greater than 10MHz, this bit must be set to use

larger (but more noisy) buffers. Another possibility is to add some wait states to slow down

the external memory interface signals (see Section 2.4).

Note: Some devices don’t have the BSZ bit and it is set to 0 by hardware. Please refer to

the datasheet.

– Data Strobe 2 Enable (DS2EN bit 5): Large Memory Model option. Setting this bit enables

the second Address Strobe pin DS2n. In this case, DSn is used when the upper memory

block is addressed (while DS2n is forced to 1), and DS2n is used when the lower memory

block is addressed (while DSn is forced to 1).

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MODER register:

– High Impedance (HIMP bit 0): setting this bit forces the external memory interface signals

(Ports 0, 1 and ASn, DSn, RWn) into High Impedance state. This option is recommended

for program phases where only internal memory is used, in order to reduce noise. This bit

must be kept to zero when the external memory has to be accessed (permanently for a

Romless version).

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EMR2 register WARNING:

The bit 4 of the EMR2 register must be set by the user when using the external memory in-

terface. Be very careful with this bit because the reset value is 0 in some devices.