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ST9 EXTERNAL MEMORY INTERFACE CONFIGURATION

2.4 TIMING CONFIGURATION

All the different signals of the external memory interface are driven by the CPU clock

(CPUCLK). The CPU clock is the result of the Internal clock (INTCLK) divided by a prescaler.

Please refer to the RCCU (Reset and Clock Control Unit) chapter of the ST9 datasheet for fur-

ther details on the clock.

If your external memory is too slow to follow the ST9 frequency, you can slow down the ex-

ternal memory interface signals in different ways:

– Reducing only the CPUCLK frequency (through the MODER register).

– Adding wait states on the ASn and DSn signals (through EMR2 and WCR registers).

– Adding wait cycles through the WAITn external pin.

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MODER register:

The three bits PRS0, PRS1, PRS2 load the prescaler division factor for the internal clock

(INTCLK which feeds the peripherals). The resulting signal is the CPU clock which drives

the external memory interface signals. You can divide the frequency by a factor from 1 to 8,

but this slow down will also affect all the code execution, as the CPU clock feeds the core.

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EMR2 register:

This register contains the control bits used to add wait states on the Address Strobe ASn

signal. Two bits (LAS[1:0]) contains the number of clock cycles to add to the CPULCK to

stretch ASn during external lower memory block accesses, whereas two other bits

(UAS[1:0]) have the same action for external upper memory block accesses. You can add

from 0 to 3 wait states to the ASn signal.

Refer to Figure 1 to see the effect of these wait states on the various signals.

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WCR register:

This register contains the control bits used to add wait states on the Data Strobe DSn signal.

Three bits (LDS[2:0]) are used for the lower memory block accesses and three other bits

(UDS[2:0]) are used for the upper memory block accesses. You can add from 0 to 7 wait

states to the DSn signal.

Refer to Figure 1 to see the effect of these wait states on the various signals.

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WAITn external pin:

You can also add wait states using the WAITn external pin which indicates to the ST9 that

the external memory requires more time to complete the memory access cycle. This function

is enabled if the EWEN bit of the EIVR register is set.

This pin is sampled on each rising edge of the internal clock: if WAITn is active (active low),

one clock cycle is added to the memory cycle. On the following rising edge of the clock,

WAITn is sampled again to continue or finish the memory cycle stretching. If WAITn is sam-

pled active during phase T1 then ASn is stretched, while if WAITn is sampled active during

phase T2 then DSn is stretched.