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ST9 EXTERNAL MEMORY INTERFACE CONFIGURATION

Figure 5. Timing Diagram for MC =1

Note: Refer to Figure 1 for the timing diagram for MC=0

ALE

PORT9/1

3

4

5

6

7

8

9

13

14

15

16

17

/OEN stays high during the complete write cycle and /WEN stays high during the complete read cycle.

10

11

PORTO

(WRITE)

WEN

(WRITE)

OEN

(READ)

PORTO

(READ)

CPUCLK

A7-A0

D7-D0 OUT

A7-A0

A21-A8

12

T1

T2

1

2

D7-D0 IN