AN1636 datasheet(9/42 Pages) STMICROELECTRONICS

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

Figure 6. Analog multiplexer

2.3 SAMPLE AND HOLD CIRCUIT

The sample and hold circuit samples the input signal and charges the internal hold capacitor

CADC to the voltage equal to VIN through RADC. The analog pin is then disconnected and the

voltage across the capacitor is then converted to digital code using successive approximation.

Figure 7. Sample and Hold circuit

The sample and hold circuit consists of an electrically operated analog switch, internal

charging resistance and hold capacitor.

As soon as the ADC conversion starts, the electrically operated switch is closed, connecting

the hold capacitor to the analog input through the internal ADC resistance RADC. This causes

a charging current to flow into the analog input and the capacitor starts to charge. The time the

switch remains closed is decided by the fADC. It is called sampling time. The sampling time is

generally indicated in the datasheet as a multiple of fADC clock periods.

Time period tAD = 1/fADC

CH[2:0] = 010

To Sample and Hold

AIN0

AIN1

AIN7

Circuit

Analog Input

Channels

Channel selection bits = 010 selects

AIN2

\/\/\/\/\/\/

Electrically operated

switch

CADC

RADC

From Analog

Multiplexer

VSSA (Analog Ground)

VIN

AN1636 Datasheet(PDF) 9 Page - STMicroelectronics