2 Register map

Migrating applications from ST7FLITE1x to ST7FLITE1xB

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2.2

Register content differences

2.2.1

SICSR register

In the SICSR (System Integrity Control/Status Register) three new bits have been added (see

Figure 2).

LOCK32: It is set when PLL 32 MHz reaches its operating frequency

CR[1:0]: RC Oscillator Frequency Adjustment bits: These bits, as well as CR[9:2] in the RCCR

RC oscillator frequency and to obtain an accuracy of 1%. 10 bits are used for calibration of

Internal RC when compared to 8 bits in ST7FLITE1x.

Figure 2.

SICSR Register

2.2.2

PWMxCSR Register

In the PWMxCSR (PWMx Control Status Register) two new bits have been added (see Figure

3) corresponding to the One Pulse mode of the Auto reload Timer.

Figure 3.

PWMxCSR Register

2.2.3

BREAKCR Register

In the BREAKCR (Break Control Register) two new bits have been added (see Figure 4) related

to Break Input Select (External break pin or the output of the comparator) and Break Input Edge

selection.

Figure 4.

BREAKCR Register

ST7FLITE1x

ST7FLITE1xB

ST7FLITE1x

ST7FLITE1xB

ST7FLITE1x

ST7FLITE1xB