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AN2523 Datasheet(PDF) 6 Page - STMicroelectronics |
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AN2523 Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 23 page ![]() Register bit definition changes AN2523 6/23 4EMI Bus EMI_BCRx Registers: EMI Burst mode is not supported. Add PSRAM (burst) mode new control bits in the Bus Control registers: Bit 0 - BLE: Byte Lane Enable Bit 8 - BPM: Burst and Page Mode Read Selection Bit 9 - SyncReadDev : Synchronous read access device Bit 11:10 - BRLEN[1:0]: Burst Read Transfer Length Bit 16 - BMWrite : Burst mode write: Bit 17 - SyncWriteDev: Synchronous write access device. Bit 19:18 - BWLen : Burst write transfer length SCU_GPIOEMI Bit 1 - Enable EMI_BCLK clock pin (BGA package) Bit 2 - Enable EMI signals: WE/UB/LB configuration (BGA package) Table 2. Register Bit Changes Item Peripheral/ Function STR91xF STR91xFA |
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