Functional changes and silicon fixes in STR91xFA

AN2523

14/23

6.10

Flash memory

Functional Fix: Flash erase and programming

Description: The Dual Bank Flash architecture in the STR91x supports the modification

(erase or programming) of one Flash bank while the CPU is fetching codes from the other

bank (RWW - read while write operation). This feature in the STR91x is functional only when

the Flash bus clock (FMI Clock) frequency is 25 MHz or lower. At higher clock frequency, the

CPU may read incorrect code or status from the Flash banks. The Flash modification

problem affects both the dual banks and the OTP sector.

Impact: This problem is fixed in STR91xFA and the Flash memory can be erased or

programmed at 96 MHz. The workaround solution for STR91xF remains good in the

STR91xFA.