DDR overview

AN3132

6/24

Doc ID 16955 Rev 1

A clock enable, CLKE (DDR_MEM_CLKEN, SPEAr600 pin), must be high for normal

operations. Interface control signals are sampled on the rising clock edge. As SDRAM

devices are manufactured in multibyte data bus width, Data (DDR_MEM_DQ, SPEAr600

pins) is a 16-bit wide bus in SPEAr600, the data mask DM (DDR_MEM_DM [1:0],

SPEAr600 pins) provides a convenient way to selectively mask individual bytes from being

written or being driven during reads.

Some common functions include activating a row for future access, performing a read, and

precharging a row (deactivating a row, often in preparation for activating a new row).

The first requirement, for example, to read an SDRAM is to activate the desired row, on the

desired bank (DDR_MEM_BA [2:0], SPEAr600 pins). To do this, you must use an activate

command by asserting RAS for one cycle while presenting the desired bank and row

address.

The next command issued to continue the transaction is a read. However the controller must

wait a number of cycles that corresponds to the DRAM array’s row-activate to column-strobe

delay time. To use the read command, you must assert CAS and present the desired bank

select and column address, along with the auto precharge (AP) flag. A particular bank must

be selected because the multibank SDRAM architecture enables reads from any bank. In

the case of reads and writes, the assertion of AP (address line 10) tells the SDRAM to

automatically precharge the activated row after the requested transaction completes.

Precharging a row returns it to quiescent state and also clears the way for another row in the

same bank to be activated next time. A single bank cannot have more than one row active at

any given time. Once the controller issues the read command, it must wait a predetermined

number of cycles before the data is returned by the SDRAM. This delay is known as CAS

latency. The data interface contains the data strobe signal (DDR_MEM_DQS [1:0],

SPEAr600 pins). It is a bidirectional clock that is used to synchronize the reads and writes

on the data bus.

Table 2.

Basic SDRAM command set

Command

CS

RAS

CAS

WE

Address

AP/A10

Bank activate

L

L

H

H

Bank, row

A10

Read

L

H

L

H

Bank, column

L

Read with auto-

precharge

LH

LH

Bank, column

H

Write

L

H

L

L

Bank, column

L

Write with auto-

precharge

L

H

L

L

Bank, column

H

No operation

L

H

H

H

X

X

Burst terminate

L

H

H

L

X

X

Bank precharge

L

L

H

L

X

L

Precharge all banks

L

L

H

L

X

H

Mode register set

L

L

L

L

Configuration

Configuration

Auto refresh

L

L

L

H

X

X

Device deselect

H

X

X

X

X

X